From 7b14b0a3fdcd291bd393d157099026cae8a40d3e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 8 Feb 2016 20:47:09 +0100
Subject: simul: fix elaboration check for implicit signals.

---
 src/vhdl/simulate/elaboration.adb | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/vhdl/simulate')

diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb
index 234fd136a..a183916f3 100644
--- a/src/vhdl/simulate/elaboration.adb
+++ b/src/vhdl/simulate/elaboration.adb
@@ -157,6 +157,7 @@ package body Elaboration is
          T := Execute_Time_Attribute (Instance, Signal);
          Init := Create_B1_Value (False);
       end if;
+      Create_Signal (Instance, Signal);
       Sig := Create_Signal_Value (null);
       Init := Unshare (Init, Global_Pool'Access);
       Instance.Objects (Info.Slot) := Sig;
-- 
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