From 2c498db7b2702d3ad762c5a35c23bb41538331b7 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 10 Jan 2015 06:51:02 +0100 Subject: vhdl08: block configuration for if-generate statements. --- src/vhdl/translate/trans-chap1.adb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/vhdl/translate') diff --git a/src/vhdl/translate/trans-chap1.adb b/src/vhdl/translate/trans-chap1.adb index 1f0e7d3e7..5911e954f 100644 --- a/src/vhdl/translate/trans-chap1.adb +++ b/src/vhdl/translate/trans-chap1.adb @@ -785,7 +785,8 @@ package body Trans.Chap1 is when Iir_Kind_Indexed_Name | Iir_Kind_Slice_Name => Block := Get_Named_Entity (Get_Prefix (Block)); - when Iir_Kinds_Denoting_Name => + when Iir_Kinds_Denoting_Name + | Iir_Kind_Parenthesis_Name => Block := Get_Named_Entity (Block); when others => null; @@ -797,7 +798,8 @@ package body Trans.Chap1 is (El, Base_Block, Get_Info (Block)); when Iir_Kind_Generate_Statement_Body => case Get_Kind (Get_Parent (Block)) is - when Iir_Kind_If_Generate_Statement => + when Iir_Kind_If_Generate_Statement + | Iir_Kind_If_Generate_Else_Clause => Translate_If_Generate_Block_Configuration_Calls (El, Base_Info); when Iir_Kind_For_Generate_Statement => -- cgit v1.2.3