From 8d3dcfb5bf4feffd59eaf2802b824059b3d75070 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 19 Sep 2022 07:27:42 +0200 Subject: synth: rework subprogram associations (WIP) --- src/vhdl/vhdl-annotations.adb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/vhdl/vhdl-annotations.adb') diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 6957ba4e3..194341730 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -885,7 +885,9 @@ package body Vhdl.Annotations is Assoc_Inter := Inter_Chain; while Assoc /= Null_Iir loop Inter := Get_Association_Interface (Assoc, Assoc_Inter); - if Is_Copyback_Parameter (Inter) then + if Get_Kind (Assoc) /= Iir_Kind_Association_Element_By_Individual + and then Is_Copyback_Parameter (Inter) + then Create_Object_Info (Block_Info, Assoc, Kind_Object); end if; Next_Association_Interface (Assoc, Assoc_Inter); -- cgit v1.2.3