From 7a0759479a991ab9ec1e2716f34b738a0286fa9a Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 8 Feb 2023 16:51:36 +0100 Subject: synth: preliminary work for PSL endpoints --- src/vhdl/vhdl-nodes_walk.adb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/vhdl/vhdl-nodes_walk.adb') diff --git a/src/vhdl/vhdl-nodes_walk.adb b/src/vhdl/vhdl-nodes_walk.adb index 63deb3b53..b3215236d 100644 --- a/src/vhdl/vhdl-nodes_walk.adb +++ b/src/vhdl/vhdl-nodes_walk.adb @@ -159,7 +159,8 @@ package body Vhdl.Nodes_Walk is | Iir_Kind_Component_Instantiation_Statement | Iir_Kinds_Simultaneous_Statement | Iir_Kind_Psl_Default_Clock - | Iir_Kind_Psl_Declaration => + | Iir_Kind_Psl_Declaration + | Iir_Kind_Psl_Endpoint_Declaration => Status := Cb.all (Stmt); when Iir_Kind_Block_Statement => Status := Cb.all (Stmt); -- cgit v1.2.3