From 1be382f13fe7d6b94dffec14922012fd463d4d04 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 26 Dec 2022 09:25:00 +0100 Subject: simul: handle transaction attribute --- src/simul/simul-vhdl_elab.adb | 9 +++++++++ src/simul/simul-vhdl_simul.adb | 7 ++++--- 2 files changed, 13 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 5c41511d6..36bc1df23 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -360,6 +360,15 @@ package body Simul.Vhdl_Elab is No_Sensitivity_Index, No_Signal_Index, No_Connect_Index, T, Pfx)); end; + when Iir_Kind_Transaction_Attribute => + declare + Pfx : Sub_Signal_Type; + begin + Pfx := Compute_Sub_Signal (Inst, Get_Prefix (Decl)); + Gather_Signal ((Mode_Transaction, Decl, Inst, null, null, null, + No_Sensitivity_Index, No_Signal_Index, + No_Connect_Index, 0, Pfx)); + end; when Iir_Kind_Delayed_Attribute => declare T : Std_Time; diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 5e120e217..8ee08d1a0 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2786,9 +2786,10 @@ package body Simul.Vhdl_Simul is Write_Sig (E.Sig, S); Register_Prefix (E.Pfx.Typ, To_Memory_Ptr (E.Pfx)); when Mode_Transaction => - -- Create_Implicit_Signal - -- (E.Sig, E.Val, E.Time, E.Prefix, E.Kind); - raise Internal_Error; + S := Grt.Signals.Ghdl_Create_Transaction_Signal + (To_Ghdl_Value_Ptr (To_Address (E.Val))); + Write_Sig (E.Sig, S); + Register_Prefix (E.Pfx.Typ, To_Memory_Ptr (E.Pfx)); when Mode_Delayed => Create_Delayed_Signal (E.Sig, E.Val, To_Memory_Ptr (E.Pfx), E.Typ, E.Time); -- cgit v1.2.3