From 9652c2bdfe75e90784910a0dd7d0f03dd97e0067 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 28 Jun 2019 07:32:40 +0200 Subject: synth: add get_input_net helper. --- src/synth/netlists-disp_vhdl.adb | 16 ++++++++-------- src/synth/netlists-dump.adb | 2 +- src/synth/netlists-gates.ads | 8 +++++++- src/synth/netlists.adb | 5 +++++ src/synth/netlists.ads | 2 ++ src/synth/synth-expr.adb | 14 +++++++------- src/synth/synth-inference.adb | 4 ++-- 7 files changed, 32 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 9d6954b2b..37e3acdaf 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -309,13 +309,13 @@ package body Netlists.Disp_Vhdl is Put (" "); Disp_Net_Name (Get_Output (Inst, 0)); Put (" <= "); - Disp_Net_Name (Get_Driver (Get_Input (Inst, 0))); + Disp_Net_Name (Get_Input_Net (Inst, 0)); Put_Line ("; -- (output)"); when Id_Not => Put (" "); Disp_Net_Name (Get_Output (Inst, 0)); Put (" <= not "); - Disp_Net_Name (Get_Driver (Get_Input (Inst, 0))); + Disp_Net_Name (Get_Input_Net (Inst, 0)); Put_Line (";"); when Id_Const_UB32 => declare @@ -341,10 +341,10 @@ package body Netlists.Disp_Vhdl is end; when Id_Adff => declare - Clk : constant Net := Get_Driver (Get_Input (Inst, 0)); - D : constant Net := Get_Driver (Get_Input (Inst, 1)); - Rst : constant Net := Get_Driver (Get_Input (Inst, 2)); - Rst_Val : constant Net := Get_Driver (Get_Input (Inst, 3)); + Clk : constant Net := Get_Input_Net (Inst, 0); + D : constant Net := Get_Input_Net (Inst, 1); + Rst : constant Net := Get_Input_Net (Inst, 2); + Rst_Val : constant Net := Get_Input_Net (Inst, 3); O : constant Net := Get_Output (Inst, 0); begin Disp_Template @@ -360,8 +360,8 @@ package body Netlists.Disp_Vhdl is end; when Id_Dff => declare - Clk : constant Net := Get_Driver (Get_Input (Inst, 0)); - D : constant Net := Get_Driver (Get_Input (Inst, 1)); + Clk : constant Net := Get_Input_Net (Inst, 0); + D : constant Net := Get_Input_Net (Inst, 1); O : constant Net := Get_Output (Inst, 0); begin Disp_Template diff --git a/src/synth/netlists-dump.adb b/src/synth/netlists-dump.adb index dc72f80e5..d1e39b538 100644 --- a/src/synth/netlists-dump.adb +++ b/src/synth/netlists-dump.adb @@ -375,7 +375,7 @@ package body Netlists.Dump is return; when Id_Extract => - Disp_Driver (Get_Driver (Get_Input (Inst, 0))); + Disp_Driver (Get_Input_Net (Inst, 0)); Put ('['); Put_Trim (Uns32'Image (Get_Param_Uns32 (Inst, 0))); Put (']'); diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 60591bb5f..c4d96df47 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -79,11 +79,17 @@ package Netlists.Gates is -- A simple D flip-flop. The D input is stored on a rising edge of CLK. -- Q is the output. For falling edge dff, use a NOT gate on the CLK -- input. + -- Inputs: CLK, D + -- Output: Q Id_Dff : constant Module_Id := 32; + -- A DFF with an asynchronous reset. Note that the asynchronous reset -- has priority over the clock. When RST is asserted, the value is - -- set to RVAL. + -- set to RST_VAL. + -- Inputs: CLK, D, RST, RST_VAL + -- Output: Q Id_Adff : constant Module_Id := 33; + -- A simple DFF with an initial value (must be constant). This is -- for FPGAs. Id_Idff : constant Module_Id := 34; diff --git a/src/synth/netlists.adb b/src/synth/netlists.adb index 6e84e2116..af1c149f2 100644 --- a/src/synth/netlists.adb +++ b/src/synth/netlists.adb @@ -461,6 +461,11 @@ package body Netlists is return Instances_Table.Table (Inst).First_Input + Input (Idx); end Get_Input; + function Get_Input_Net (Inst : Instance; Idx : Port_Idx) return Net is + begin + return Get_Driver (Get_Input (Inst, Idx)); + end Get_Input_Net; + -- Nets function Is_Valid (N : Net) return Boolean is diff --git a/src/synth/netlists.ads b/src/synth/netlists.ads index f84f0c78e..a3c6cfe7c 100644 --- a/src/synth/netlists.ads +++ b/src/synth/netlists.ads @@ -235,6 +235,8 @@ package Netlists is function Get_Param_Uns32 (Inst : Instance; Param : Param_Idx) return Uns32; procedure Set_Param_Uns32 (Inst : Instance; Param : Param_Idx; Val : Uns32); + function Get_Input_Net (Inst : Instance; Idx : Port_Idx) return Net; + -- Input function Get_Input_Parent (I : Input) return Instance; function Get_Parent (I : Input) return Instance renames Get_Input_Parent; diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index dd759362d..8d94876f5 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -920,8 +920,8 @@ package body Synth.Expr is loop Inst := Get_Parent (Inp); if Get_Id (Get_Module (Inst)) = Id_Add then - Val_I0 := Get_Driver (Get_Input (Inst, 0)); - Val_I1 := Get_Driver (Get_Input (Inst, 1)); + Val_I0 := Get_Input_Net (Inst, 0); + Val_I1 := Get_Input_Net (Inst, 1); if Is_Const (Val_I0) then Addend := Addend + Get_Const (Val_I0) * Factor; Inp := Val_I1; @@ -933,8 +933,8 @@ package body Synth.Expr is return; end if; elsif Get_Id (Get_Module (Inst)) = Id_Sub then - Val_I0 := Get_Driver (Get_Input (Inst, 0)); - Val_I1 := Get_Driver (Get_Input (Inst, 1)); + Val_I0 := Get_Input_Net (Inst, 0); + Val_I1 := Get_Input_Net (Inst, 1); if Is_Const (Val_I1) then Addend := Addend - Get_Const (Val_I1) * Factor; Inp := Val_I0; @@ -943,8 +943,8 @@ package body Synth.Expr is return; end if; elsif Get_Id (Get_Module (Inst)) = Id_Mul then - Val_I0 := Get_Driver (Get_Input (Inst, 0)); - Val_I1 := Get_Driver (Get_Input (Inst, 1)); + Val_I0 := Get_Input_Net (Inst, 0); + Val_I1 := Get_Input_Net (Inst, 1); if Is_Const (Val_I0) then Factor := Factor * Get_Const (Val_I0); Inp := Val_I1; @@ -956,7 +956,7 @@ package body Synth.Expr is return; end if; elsif Get_Id (Get_Module (Inst)) = Id_Uextend then - Inp := Get_Driver (Get_Input (Inst, 0)); + Inp := Get_Input_Net (Inst, 0); else -- Cannot decompose it. return; diff --git a/src/synth/synth-inference.adb b/src/synth/synth-inference.adb index 8df96d677..cb7a0ee41 100644 --- a/src/synth/synth-inference.adb +++ b/src/synth/synth-inference.adb @@ -82,7 +82,7 @@ package body Synth.Inference is -- Assume the condition is canonicalized, ie of the form: -- CLK and EXPR. -- FIXME: do it! - return Has_Clock (Get_Driver (Get_Input (Inst, 0))); + return Has_Clock (Get_Input_Net (Inst, 0)); when others => return False; end case; @@ -154,7 +154,7 @@ package body Synth.Inference is case Get_Id (Inst) is when Id_Edge => -- Get rid of the edge gate, just return the signal. - Clk := Get_Driver (Get_Input (Inst, 0)); + Clk := Get_Input_Net (Inst, 0); when Id_And => -- Assume the condition is canonicalized, ie of the form: -- CLK and EXPR. -- cgit v1.2.3