From a08e8ce832701dd0832330e783009b20b34f6782 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 21 Oct 2019 21:07:51 +0200 Subject: vhdl-sem_decls: add comment. --- src/vhdl/vhdl-sem_decls.adb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb index 0f173d923..0f6cb17e7 100644 --- a/src/vhdl/vhdl-sem_decls.adb +++ b/src/vhdl/vhdl-sem_decls.adb @@ -2057,6 +2057,9 @@ package body Vhdl.Sem_Decls is -- If IS_GLOBAL is set, then declarations may be seen outside of unit. -- This must be set for entities and packages (except when -- Flags.Flag_Whole_Analyze is set). + -- This controls whether a type is used for a signal. + -- When Flag_Whole_Analyze is false, we are conservative and assume + -- that any global type is used for a signal (when allowed). Is_Global : Boolean; begin case Get_Kind (Parent) is -- cgit v1.2.3