From daa29e96da7ee3557d71005cd31c554f5fd74f34 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 16 Sep 2022 04:24:58 +0200 Subject: simul: improve error handling during elaboration --- src/ghdldrv/ghdlsimul.adb | 10 +++++----- src/simul/simul-vhdl_elab.adb | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb index 41dac66d2..bdc5ef6c8 100644 --- a/src/ghdldrv/ghdlsimul.adb +++ b/src/ghdldrv/ghdlsimul.adb @@ -94,16 +94,16 @@ package body Ghdlsimul is Inst := Elab.Vhdl_Insts.Elab_Top_Unit (Lib_Unit); if Errorout.Nbr_Errors > 0 then - if Grt.Errors.Expect_Failure then - return; - else - raise Errorout.Compilation_Error; - end if; + raise Errorout.Compilation_Error; end if; Simul.Vhdl_Elab.Gather_Processes (Inst); Simul.Vhdl_Elab.Elab_Processes; + if Errorout.Nbr_Errors > 0 then + raise Errorout.Compilation_Error; + end if; + if False then Elab.Vhdl_Debug.Disp_Hierarchy (Inst, False, True); end if; diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 4296008eb..01cfc6b9a 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -984,6 +984,7 @@ package body Simul.Vhdl_Elab is Processes_Table.Table (I).Inst := Proc_Inst; Elab.Vhdl_Decls.Elab_Declarations (Proc_Inst, Get_Declaration_Chain (Proc), True); + exit when Is_Error (Proc_Inst); end if; end loop; Instance_Pool := null; -- cgit v1.2.3