From f4976c9f41903ef09b0225977129660a6391042b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 29 Dec 2013 03:27:39 +0100
Subject: Add gna tests

---
 testsuite/gna/bug21332/twoscomplement.vhdl | 48 ++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 testsuite/gna/bug21332/twoscomplement.vhdl

(limited to 'testsuite/gna/bug21332/twoscomplement.vhdl')

diff --git a/testsuite/gna/bug21332/twoscomplement.vhdl b/testsuite/gna/bug21332/twoscomplement.vhdl
new file mode 100644
index 000000000..639f04981
--- /dev/null
+++ b/testsuite/gna/bug21332/twoscomplement.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+entity twoscompliment is
+      generic
+      (
+              Nbits : positive := 8 
+       );
+ port 
+( 
+           --Inputs
+           A : in std_logic_vector (Nbits-1 downto 0);
+           --Outputs
+           Y : out std_logic_vector (Nbits downto 0)
+);
+end twoscompliment;
+
+architecture twoscompliment_v1 of twoscompliment is
+    constant ONE:   UNSIGNED(Y'RANGE) := (0 => '1', others => '0');
+begin
+     Y <= std_logic_vector(unsigned (not A) + ONE);
+end twoscompliment_v1;
+
+architecture twoscompliment_v2 of twoscompliment is
+signal temp : std_logic_vector(Nbits-1 downto 0);
+begin
+  temp <= not A;
+  Y    <= std_logic_vector(unsigned(temp) + 1);
+end twoscompliment_v2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test is
+end entity;
+
+architecture foo of test is
+    -- counts on default value for Nbits in DUT = 8)
+    signal A:   std_logic_vector (7 downto 0) := (0=>'1', others => '0');  -- ONE
+    signal Y:   std_logic_vector ( 8 downto 0);
+begin
+    DUT: entity work.twoscompliment(twoscompliment_v2)
+    port map (
+        A => A,
+        Y => Y
+    );
+        
+end architecture;
\ No newline at end of file
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