From 66e31d6d8c4faab0aeadee87298f13a3b67adbfb Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 2 Apr 2016 07:40:37 +0200 Subject: Add testcase for issue50. --- testsuite/gna/issue50/idct.d/add_483.vhd | 33 ++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 testsuite/gna/issue50/idct.d/add_483.vhd (limited to 'testsuite/gna/issue50/idct.d/add_483.vhd') diff --git a/testsuite/gna/issue50/idct.d/add_483.vhd b/testsuite/gna/issue50/idct.d/add_483.vhd new file mode 100644 index 000000000..92b5fde0e --- /dev/null +++ b/testsuite/gna/issue50/idct.d/add_483.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_483 is + port ( + result : out std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0) + ); +end add_483; + +architecture augh of add_483 is + + signal carry_inA : std_logic_vector(33 downto 0); + signal carry_inB : std_logic_vector(33 downto 0); + signal carry_res : std_logic_vector(33 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + result <= carry_res(32 downto 1); + +end architecture; -- cgit v1.2.3