From 53d4861c853bc057b5db337f617d0311bc3a1e85 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <gingold@adacore.com>
Date: Tue, 22 Dec 2015 16:14:35 +0100
Subject: Add testcase for ticket104.

---
 testsuite/gna/ticket104/bug_tb.vhd   | 40 ++++++++++++++++++++++++++++++++++++
 testsuite/gna/ticket104/testsuite.sh | 10 +++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 testsuite/gna/ticket104/bug_tb.vhd
 create mode 100755 testsuite/gna/ticket104/testsuite.sh

(limited to 'testsuite/gna/ticket104')

diff --git a/testsuite/gna/ticket104/bug_tb.vhd b/testsuite/gna/ticket104/bug_tb.vhd
new file mode 100644
index 000000000..8abb61ca5
--- /dev/null
+++ b/testsuite/gna/ticket104/bug_tb.vhd
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity bug_tb is
+
+end bug_tb;
+
+-------------------------------------------------------------------------------
+
+architecture test of bug_tb is
+
+  type t_test_vec is array (10 downto -1) of std_logic;
+  signal test_vec : t_test_vec := (others => '0');
+
+  -- clock
+  signal Clk : std_logic := '1';
+
+  procedure pr_vec (
+    vec : in std_logic_vector) is
+  begin  -- procedure pr_vec
+    for i in vec'range loop
+      report "bit: " & integer'image(i) & "=" & std_logic'image(vec(i)) severity note;
+    end loop;  -- i
+  end procedure pr_vec;
+  
+begin  -- test
+
+  -- clock generation
+  Clk <= not Clk after 10 ns;
+
+  -- waveform generation
+  WaveGen_Proc : process
+  begin
+    wait until rising_edge(Clk);
+    pr_vec(std_logic_vector(test_vec));
+    wait;
+  end process WaveGen_Proc;
+
+end test;
+
diff --git a/testsuite/gna/ticket104/testsuite.sh b/testsuite/gna/ticket104/testsuite.sh
new file mode 100755
index 000000000..d0db007ca
--- /dev/null
+++ b/testsuite/gna/ticket104/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze bug_tb.vhd
+elab_simulate_failure bug_tb
+
+clean
+
+echo "Test successful"
-- 
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