From 11e5e62f06e225a5f39cf31581063bd469a05064 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 12 Jun 2020 20:07:41 +0200
Subject: testsuite/gna: complete test for #1364

---
 testsuite/gna/issue1364/mwe.vhdl      | 38 ---------------------------
 testsuite/gna/issue1364/mwe_aggr.vhdl | 38 +++++++++++++++++++++++++++
 testsuite/gna/issue1364/mwe_case.vhdl | 48 +++++++++++++++++++++++++++++++++++
 testsuite/gna/issue1364/testsuite.sh  |  4 ++-
 4 files changed, 89 insertions(+), 39 deletions(-)
 delete mode 100644 testsuite/gna/issue1364/mwe.vhdl
 create mode 100644 testsuite/gna/issue1364/mwe_aggr.vhdl
 create mode 100644 testsuite/gna/issue1364/mwe_case.vhdl

(limited to 'testsuite/gna')

diff --git a/testsuite/gna/issue1364/mwe.vhdl b/testsuite/gna/issue1364/mwe.vhdl
deleted file mode 100644
index 9657e98b5..000000000
--- a/testsuite/gna/issue1364/mwe.vhdl
+++ /dev/null
@@ -1,38 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity mwe is
-	port(
-		n_rst_i		: in std_logic;
-		clk_i     	: in std_logic	
-	);
-end entity mwe;
-
-architecture arch of mwe is
-
--- I declare a new type which is an array of buses 
-type my_new_type is array(natural range <>) of std_logic_vector(31 downto 0);
-
--- Then I declare a constant of that new type 
-constant constant_of_my_new_type : my_new_type (0 to 7) := ((others=>(others => '0')));
-
-signal signal_of_my_new_type 		: my_new_type (0 to 7);
-
-begin
-
-process(clk_i)
-begin
-	
-	-- if Reset low then signal_of_my_new_type = constant_of_my_new_type
-	-- else, signal_of_my_new_type is filled with one at the next clock rising edge
-
-	if n_rst_i = '0' then
-		signal_of_my_new_type <= constant_of_my_new_type;
-	elsif rising_edge(clk_i) then
-		signal_of_my_new_type <= ((others=>(others => '1')));
-	end if;
-		
-end process;
-
-end architecture;
diff --git a/testsuite/gna/issue1364/mwe_aggr.vhdl b/testsuite/gna/issue1364/mwe_aggr.vhdl
new file mode 100644
index 000000000..9657e98b5
--- /dev/null
+++ b/testsuite/gna/issue1364/mwe_aggr.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mwe is
+	port(
+		n_rst_i		: in std_logic;
+		clk_i     	: in std_logic	
+	);
+end entity mwe;
+
+architecture arch of mwe is
+
+-- I declare a new type which is an array of buses 
+type my_new_type is array(natural range <>) of std_logic_vector(31 downto 0);
+
+-- Then I declare a constant of that new type 
+constant constant_of_my_new_type : my_new_type (0 to 7) := ((others=>(others => '0')));
+
+signal signal_of_my_new_type 		: my_new_type (0 to 7);
+
+begin
+
+process(clk_i)
+begin
+	
+	-- if Reset low then signal_of_my_new_type = constant_of_my_new_type
+	-- else, signal_of_my_new_type is filled with one at the next clock rising edge
+
+	if n_rst_i = '0' then
+		signal_of_my_new_type <= constant_of_my_new_type;
+	elsif rising_edge(clk_i) then
+		signal_of_my_new_type <= ((others=>(others => '1')));
+	end if;
+		
+end process;
+
+end architecture;
diff --git a/testsuite/gna/issue1364/mwe_case.vhdl b/testsuite/gna/issue1364/mwe_case.vhdl
new file mode 100644
index 000000000..5cb1f6cb4
--- /dev/null
+++ b/testsuite/gna/issue1364/mwe_case.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mwe is
+	port(
+		n_rst_i		: in std_logic;
+		clk_i     	: in std_logic	
+	);
+end entity mwe;
+
+architecture arch of mwe is
+
+signal counter 					: unsigned(2 DOWNTO 0);
+
+signal weird_clock 				: std_logic;
+signal weird_clock_parenthesis 	: std_logic;
+
+begin
+
+process(clk_i)
+begin
+	
+	-- if Reset low then weird_clock = 0
+	-- else, weird_clock is set to one for the counter = 1 or 3 or 6
+
+	if n_rst_i = '0' then
+		counter <= (others => '0');
+		weird_clock <= '0';
+		weird_clock_parenthesis <= '0';
+	elsif rising_edge(clk_i) then
+		counter <= counter+1;
+		case (counter) is
+			when "001"  => weird_clock <= '1';
+			when "011"  => weird_clock <= '1';
+			when "110"  => weird_clock <= '1';
+			when others => weird_clock <= '0';
+		end case;
+
+		case counter is
+			when "010"  => weird_clock_parenthesis <= '1';
+			when "101"  => weird_clock_parenthesis <= '1';
+			when others => weird_clock_parenthesis <= '0';
+		end case;
+		
+	end if;
+  end process;
+end;
diff --git a/testsuite/gna/issue1364/testsuite.sh b/testsuite/gna/issue1364/testsuite.sh
index 141fb1837..358efb5ab 100755
--- a/testsuite/gna/issue1364/testsuite.sh
+++ b/testsuite/gna/issue1364/testsuite.sh
@@ -2,7 +2,9 @@
 
 . ../../testenv.sh
 
-analyze_failure mwe.vhdl
+analyze_failure mwe_aggr.vhdl
+analyze -frelaxed mwe_aggr.vhdl
+analyze mwe_case.vhdl
 
 clean
 
-- 
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