From 25fe65a7dd9172d4368ead88393c43c3f2329fdf Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 2 Nov 2022 18:44:40 +0100
Subject: testsuite/gna: add a test for #2238

---
 testsuite/gna/issue2238/port_map2.vhdl | 18 ++++++++++++++++++
 testsuite/gna/issue2238/testsuite.sh   |  9 +++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 testsuite/gna/issue2238/port_map2.vhdl
 create mode 100755 testsuite/gna/issue2238/testsuite.sh

(limited to 'testsuite/gna')

diff --git a/testsuite/gna/issue2238/port_map2.vhdl b/testsuite/gna/issue2238/port_map2.vhdl
new file mode 100644
index 000000000..f2b215253
--- /dev/null
+++ b/testsuite/gna/issue2238/port_map2.vhdl
@@ -0,0 +1,18 @@
+library IEEE ;
+use ieee.std_logic_1164.all ; 
+use ieee.numeric_std.all ; 
+
+entity PortMap2 is
+end entity PortMap2 ;
+architecture t1 of PortMap2 is 
+  component fred is
+    port (A : in signed(7 downto 0) ; B : out signed (7 downto 0) ) ; 
+  end component fred ; 
+  
+  signal Result : signed (7 downto 0) ; 
+begin
+
+  fred1 :  fred 
+    port map (A => signed'("00001111"),  B => Result ) ; 
+
+end architecture t1 ;
diff --git a/testsuite/gna/issue2238/testsuite.sh b/testsuite/gna/issue2238/testsuite.sh
new file mode 100755
index 000000000..57621960b
--- /dev/null
+++ b/testsuite/gna/issue2238/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze port_map2.vhdl
+
+clean
+
+echo "Test successful"
-- 
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