From 4895ba09c84b53873d229ff395ff2d1cc47695db Mon Sep 17 00:00:00 2001 From: Ondrej Ille Date: Sat, 20 Mar 2021 17:26:51 +0100 Subject: testsuite: Add gna for 1690. --- testsuite/gna/issue1690/testsuite.sh | 11 +++++++++ testsuite/gna/issue1690/top.vhd | 48 ++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 testsuite/gna/issue1690/testsuite.sh create mode 100644 testsuite/gna/issue1690/top.vhd (limited to 'testsuite/gna') diff --git a/testsuite/gna/issue1690/testsuite.sh b/testsuite/gna/issue1690/testsuite.sh new file mode 100644 index 000000000..cf12c78ea --- /dev/null +++ b/testsuite/gna/issue1690/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS='-Wpsl-uncovered --std=08 -fpsl' +analyze top.vhd +elab_simulate tb_top + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue1690/top.vhd b/testsuite/gna/issue1690/top.vhd new file mode 100644 index 000000000..ccd70a96f --- /dev/null +++ b/testsuite/gna/issue1690/top.vhd @@ -0,0 +1,48 @@ + +Library ieee; +use ieee.std_logic_1164.all; + +entity tb_top is +end entity; + + +architecture tb of tb_top is + + signal a,b,c : std_logic; + signal clk_sys : std_logic; + +begin + + gen_clock_proc : process + begin + clk_sys <= '1'; + wait for 5 ns; + clk_sys <= '0'; + wait for 5 ns; + end process; + + test_proc : process + begin + a <= '0'; + b <= '0'; + c <= '0'; + wait until rising_edge(clk_sys); + a <= '1'; + wait until rising_edge(clk_sys); + a <= '0'; + b <= '1'; + wait until rising_edge(clk_sys); + b <= '0'; + c <= '1'; + wait until rising_edge(clk_sys); + + std.env.finish; + end process; + + + -- psl default clock is rising_edge(clk_sys); + + -- psl cov_simult_a_b_c : cover {a = '1' and b = '1' and c = '1'}; + +end architecture tb; + -- cgit v1.2.3