From dc6a82418653ce5b732d2bc26b393d3259fd93d5 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 31 Oct 2016 09:09:23 +0100
Subject: Add testcase for #176

---
 testsuite/gna/issue176/t2.vhdl      | 11 +++++++++++
 testsuite/gna/issue176/test.vhdl    | 21 +++++++++++++++++++++
 testsuite/gna/issue176/testsuite.sh |  9 +++++++++
 3 files changed, 41 insertions(+)
 create mode 100644 testsuite/gna/issue176/t2.vhdl
 create mode 100644 testsuite/gna/issue176/test.vhdl
 create mode 100755 testsuite/gna/issue176/testsuite.sh

(limited to 'testsuite/gna')

diff --git a/testsuite/gna/issue176/t2.vhdl b/testsuite/gna/issue176/t2.vhdl
new file mode 100644
index 000000000..419094d56
--- /dev/null
+++ b/testsuite/gna/issue176/t2.vhdl
@@ -0,0 +1,11 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t2 is
+end t2;
+
+architecture behav of t2 is
+  constant my_const : std_ulogic_vector := "01XWL";
+  constant my_str : string := "Hello";
+begin
+end;
diff --git a/testsuite/gna/issue176/test.vhdl b/testsuite/gna/issue176/test.vhdl
new file mode 100644
index 000000000..1fbb98238
--- /dev/null
+++ b/testsuite/gna/issue176/test.vhdl
@@ -0,0 +1,21 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity testcase is
+	generic ( DATA_WIDTH : natural := 32 );
+
+	port (
+		ce        : in  std_logic;
+		clk       : in  std_logic
+	);
+end entity testcase;
+
+architecture behaviour of testcase is
+
+	signal reg_tmode : unsigned(1 downto 0) := "00";
+
+begin
+
+
+end behaviour;
diff --git a/testsuite/gna/issue176/testsuite.sh b/testsuite/gna/issue176/testsuite.sh
new file mode 100755
index 000000000..e8562e586
--- /dev/null
+++ b/testsuite/gna/issue176/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+$GHDL --file-to-xml t2.vhdl | grep -q "01X"
+$GHDL --file-to-xml test.vhdl | grep -q '"00"'
+clean
+
+echo "Test successful"
-- 
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