From 7ae0931d3e6733ceb76f1d884e282d7d6b5fb489 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 29 Dec 2022 23:18:42 +0100 Subject: Improved VHDL example project. --- testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl') diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl index 1a40718aa..f67f99c72 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl @@ -18,4 +18,16 @@ package StopWatch_pkg is end record; type T_STOPWATCH_CONFIGURATION is array(natural range <>) of T_DIGIT_CONFIGURATION; + + -- Encoder that translates from 4-bit binary (BCD) to 7-segment code. + -- + -- In addition, an optional dot input is supported. + component seg7_Encoder is + port ( + BCDValue : in T_BCD; + Dot : in std_logic := '0'; + + Seg7Code : out std_logic_vector(7 downto 0) + ); + end component; end package; -- cgit v1.2.3