From 7ae0931d3e6733ceb76f1d884e282d7d6b5fb489 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 29 Dec 2022 23:18:42 +0100 Subject: Improved VHDL example project. --- testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl') diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl index 7bb6e9cd9..08046e2cc 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl @@ -59,7 +59,7 @@ begin Board_Reset <= not NexysA7_GPIO_Button_Reset_n; -- Debounce input signals - deb: entity work.Debouncer + deb: component Debouncer generic map ( CLOCK_PERIOD => CLOCK_PERIOD, BITS => 2 @@ -100,7 +100,7 @@ begin ); -- 7-segment display - display: entity work.seg7_Display + display: configuration seg7_Display_cfg generic map ( CLOCK_PERIOD => CLOCK_PERIOD, DIGITS => Digits'length -- cgit v1.2.3