From ab2e4632eb987f9173f56bab05adf18308e060fb Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 25 Feb 2020 01:23:31 +0100 Subject: testsuite/synth: add test case for #1140 --- testsuite/synth/issue1140/tb_ent.vhdl | 49 +++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 testsuite/synth/issue1140/tb_ent.vhdl (limited to 'testsuite/synth/issue1140/tb_ent.vhdl') diff --git a/testsuite/synth/issue1140/tb_ent.vhdl b/testsuite/synth/issue1140/tb_ent.vhdl new file mode 100644 index 000000000..85d370e2e --- /dev/null +++ b/testsuite/synth/issue1140/tb_ent.vhdl @@ -0,0 +1,49 @@ +entity tb_ent is +end tb_ent; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_ent is + -- Interrupt mapping register: + signal iar : unsigned(15 downto 0) := "0000000010010000"; + signal ipend : unsigned(3 downto 0) := (others => '0'); + signal irq : unsigned(3 downto 0); + signal clk : std_logic := '0'; +begin + dut: entity work.ent + generic map (NUM_CHANNELS => 4) + port map (iar => iar, ipend => ipend, irq => irq, clk => clk); + + process + begin + clk <= not clk; + wait for 1 ns; + end process; + +stim: + process + begin + wait for 10 ns; + ipend(0) <= '1'; + wait for 10 ns; + ipend(1) <= '1'; + wait for 10 ns; + ipend(2) <= '1'; + wait for 10 ns; + ipend <= (others => '0'); + + wait for 10 ns; + ipend(3) <= '1'; + wait for 10 ns; + ipend(2) <= '1'; + wait for 10 ns; + ipend(1) <= '1'; + wait for 10 ns; + ipend <= (others => '0'); + + wait; + end process; + +end behav; -- cgit v1.2.3