From 27824b89e270759419cf9854e7470388acfa7716 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 20 Mar 2020 07:44:09 +0100
Subject: testsuite/synth: add tests for #1163

---
 testsuite/synth/issue1163/bug3.vhdl | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 testsuite/synth/issue1163/bug3.vhdl

(limited to 'testsuite/synth/issue1163/bug3.vhdl')

diff --git a/testsuite/synth/issue1163/bug3.vhdl b/testsuite/synth/issue1163/bug3.vhdl
new file mode 100644
index 000000000..071972d37
--- /dev/null
+++ b/testsuite/synth/issue1163/bug3.vhdl
@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+    port(index : in integer range 0 to 1);
+end bug;
+
+architecture behav of bug is
+
+    type foobar is record
+        foo : std_logic;
+        bar : std_logic_vector(1 downto 0);
+    end record;
+
+    -- Changing the order works:
+    --type foobar is record
+    --    bar : std_logic_vector(1 downto 0);
+    --    foo : std_logic;
+    --end record;
+
+    type foobar_array is array (0 to 1) of foobar;
+
+    signal s_foobar : foobar_array;
+begin
+    s_foobar(index).bar(0) <= '0';
+end architecture;
-- 
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