From cc944ffc3e99557a72f177e2d0b855b079e15bf0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 19 Mar 2020 18:29:28 +0100
Subject: testsuite/synth: add a test for #1164

---
 testsuite/synth/issue1164/bug.vhdl | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 testsuite/synth/issue1164/bug.vhdl

(limited to 'testsuite/synth/issue1164/bug.vhdl')

diff --git a/testsuite/synth/issue1164/bug.vhdl b/testsuite/synth/issue1164/bug.vhdl
new file mode 100644
index 000000000..a0b9ac969
--- /dev/null
+++ b/testsuite/synth/issue1164/bug.vhdl
@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+	port(
+		clk                     :  in std_ulogic;
+		reset_n                 :  in std_ulogic
+	);
+end bug;
+
+architecture behav of bug is
+	component comp is
+	port (		
+		data : in std_ulogic_vector
+	);
+	end component;
+	
+	type fifo_rdata_t is array (0 to 0) of std_ulogic_vector(4*8-1 downto 0);
+	signal fifo_rdata : fifo_rdata_t;
+begin
+	c : comp
+	port map(
+		data => fifo_rdata(0)
+	);
+end architecture;
+
-- 
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