From 51fb29f988e3d4d2cf2192fcc0f0a64d07f9d91e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 19 Jul 2019 06:51:12 +0200
Subject: synth: add testcase from issue8

---
 testsuite/synth/issue8/test2.vhdl | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 testsuite/synth/issue8/test2.vhdl

(limited to 'testsuite/synth/issue8/test2.vhdl')

diff --git a/testsuite/synth/issue8/test2.vhdl b/testsuite/synth/issue8/test2.vhdl
new file mode 100644
index 000000000..dca1601bb
--- /dev/null
+++ b/testsuite/synth/issue8/test2.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test2 is
+  port (led: out std_logic_vector (7 downto 0));
+end test2;
+
+architecture synth of test2 is
+
+begin
+  led(7) <= '0';
+  led(6) <= '1';
+--  led(5) <= '0';
+--  led(3 downto 0) <= x"9";
+end synth;
-- 
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