From 51fb29f988e3d4d2cf2192fcc0f0a64d07f9d91e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 19 Jul 2019 06:51:12 +0200
Subject: synth: add testcase from issue8

---
 testsuite/synth/issue8/vector8_test1.vhdl | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 testsuite/synth/issue8/vector8_test1.vhdl

(limited to 'testsuite/synth/issue8/vector8_test1.vhdl')

diff --git a/testsuite/synth/issue8/vector8_test1.vhdl b/testsuite/synth/issue8/vector8_test1.vhdl
new file mode 100644
index 000000000..585d003b0
--- /dev/null
+++ b/testsuite/synth/issue8/vector8_test1.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector8_test1 is
+  port (led7: out std_logic);
+end vector8_test1;
+
+architecture synth of vector8_test1 is
+
+signal v : std_logic_vector(7 downto 0);
+
+begin
+  v(7) <= '1';
+  led7 <= v(7);
+end synth;
-- 
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