From d6dfa7a2b0742b411bb992fc143e7ada382498b0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 30 Sep 2019 20:27:32 +0200
Subject: testsuite/synth: add testcase for #951

---
 testsuite/synth/issue951/ent.vhdl | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 testsuite/synth/issue951/ent.vhdl

(limited to 'testsuite/synth/issue951/ent.vhdl')

diff --git a/testsuite/synth/issue951/ent.vhdl b/testsuite/synth/issue951/ent.vhdl
new file mode 100644
index 000000000..1d6ae9a72
--- /dev/null
+++ b/testsuite/synth/issue951/ent.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+    port (
+        clk : in std_logic;
+        enable : in std_logic;
+        i : in std_logic;
+        o : out std_logic
+    );
+end;
+
+architecture a of ent is
+begin
+    process(clk)
+    begin
+        -- works:
+        --if rising_edge(clk) and enable = '1' then
+        if enable = '1' and rising_edge(clk) then
+            o <= i;
+        end if;
+    end process;
+end;
-- 
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