From 419d542accc0a0bd5f3daa833f202043ce6f480c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 8 Sep 2019 08:36:02 +0200
Subject: testsuite/synth: rename arr02 to mem01

---
 testsuite/synth/mem01/tb_rom1.vhdl | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 testsuite/synth/mem01/tb_rom1.vhdl

(limited to 'testsuite/synth/mem01/tb_rom1.vhdl')

diff --git a/testsuite/synth/mem01/tb_rom1.vhdl b/testsuite/synth/mem01/tb_rom1.vhdl
new file mode 100644
index 000000000..4a7f96d29
--- /dev/null
+++ b/testsuite/synth/mem01/tb_rom1.vhdl
@@ -0,0 +1,38 @@
+entity tb_rom1 is
+end tb_rom1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_rom1 is
+  signal addr : std_logic_vector(3 downto 0);
+  signal dat : std_logic_vector(7 downto 0);
+begin
+  dut: entity work.rom1
+    port map (addr, dat);
+
+  process
+  begin
+    addr <= "0000";
+    wait for 1 ns;
+    assert dat = x"00" severity failure;
+    
+    addr <= "0101";
+    wait for 1 ns;
+    assert dat = x"41" severity failure;
+    
+    addr <= "1100";
+    wait for 1 ns;
+    assert dat = x"fc" severity failure;
+    
+    addr <= "1011";
+    wait for 1 ns;
+    assert dat = x"fb" severity failure;
+    
+    addr <= "0010";
+    wait for 1 ns;
+    assert dat = x"02" severity failure;
+    
+    wait;
+  end process;
+end behav;
-- 
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