From e0281345a5437282f287568b6fafa8519512b9dd Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 23 Jul 2019 07:34:52 +0200 Subject: synth: add testcase for previous commit. --- testsuite/synth/slice01/slice01.vhdl | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 testsuite/synth/slice01/slice01.vhdl (limited to 'testsuite/synth/slice01/slice01.vhdl') diff --git a/testsuite/synth/slice01/slice01.vhdl b/testsuite/synth/slice01/slice01.vhdl new file mode 100644 index 000000000..0aaeced74 --- /dev/null +++ b/testsuite/synth/slice01/slice01.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity slice01 is + generic (w: natural := 4); + port (rst : std_logic; + clk : std_logic; + di : std_logic; + do : out std_logic_vector (w - 1 downto 0)); +end slice01; + +architecture behav of slice01 is + signal r : std_logic_vector (w - 1 downto 0); +begin + do <= r; + + process(clk) + begin + if rising_edge (clk) then + if rst = '1' then + r <= (others => '0'); + else + r (w - 2 downto 0) <= r (w - 1 downto 1); + r (w - 1) <= di; + end if; + end if; + end process; +end behav; -- cgit v1.2.3