From 8ba9adc3f24e9761c5aae4810fae3f4529ffa9f1 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 1 Nov 2019 18:51:37 +0100
Subject: testsuite/synth: add a test for inout variable

---
 testsuite/synth/subprg01/tb_subprg01.vhdl | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 testsuite/synth/subprg01/tb_subprg01.vhdl

(limited to 'testsuite/synth/subprg01/tb_subprg01.vhdl')

diff --git a/testsuite/synth/subprg01/tb_subprg01.vhdl b/testsuite/synth/subprg01/tb_subprg01.vhdl
new file mode 100644
index 000000000..de60ca324
--- /dev/null
+++ b/testsuite/synth/subprg01/tb_subprg01.vhdl
@@ -0,0 +1,25 @@
+entity tb_subprg01 is
+end tb_subprg01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_subprg01 is
+  signal a, na : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.subprg01
+    port map (a, na);
+
+  process
+  begin
+    a <= x"0";
+    wait for 1 ns;
+    assert na = x"f" severity failure;
+
+    a <= x"5";
+    wait for 1 ns;
+    assert na = x"a" severity failure;
+
+    wait;
+  end process;
+end behav;
-- 
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