From 6e9336d11dfc4f53dba234e1f02a2b0172461e0c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 25 Sep 2019 20:39:46 +0200 Subject: testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues. --- testsuite/synth/synth33/int_test2.vhdl | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 testsuite/synth/synth33/int_test2.vhdl (limited to 'testsuite/synth/synth33/int_test2.vhdl') diff --git a/testsuite/synth/synth33/int_test2.vhdl b/testsuite/synth/synth33/int_test2.vhdl new file mode 100644 index 000000000..eb43306c4 --- /dev/null +++ b/testsuite/synth/synth33/int_test2.vhdl @@ -0,0 +1,31 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity int_test2 is + generic ( + INT_MIN : integer range 1 to 8 := 1; + INT_MAX : integer range 1 to 8 := 8 + ); + port ( + clk : in std_logic; + a : in integer range INT_MIN to INT_MAX; + b : out integer range INT_MIN to INT_MAX + ); +end int_test2; + +architecture rtl of int_test2 is + signal int : integer range INT_MIN to INT_MAX; +begin + process (clk) + begin + if rising_edge (clk) then + if a < INT_MAX then + int <= a + 1; + else + int <= INT_MIN * 2; + end if; + end if; + end process; + b <= int; +end rtl; + -- cgit v1.2.3