From 6e9336d11dfc4f53dba234e1f02a2b0172461e0c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 25 Sep 2019 20:39:46 +0200 Subject: testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues. --- testsuite/synth/synth8/tb_vector8_test1.vhdl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 testsuite/synth/synth8/tb_vector8_test1.vhdl (limited to 'testsuite/synth/synth8/tb_vector8_test1.vhdl') diff --git a/testsuite/synth/synth8/tb_vector8_test1.vhdl b/testsuite/synth/synth8/tb_vector8_test1.vhdl new file mode 100644 index 000000000..0a37884d5 --- /dev/null +++ b/testsuite/synth/synth8/tb_vector8_test1.vhdl @@ -0,0 +1,19 @@ +entity tb_vector8_test1 is +end tb_vector8_test1; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_vector8_test1 is + signal r : std_logic; +begin + dut: entity work.vector8_test1 + port map (r); + + process + begin + wait for 1 ns; + assert r = '1' severity failure; + wait; + end process; +end behav; -- cgit v1.2.3