From 6e9336d11dfc4f53dba234e1f02a2b0172461e0c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 25 Sep 2019 20:39:46 +0200
Subject: testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.

---
 testsuite/synth/synth8/test4.vhdl | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 testsuite/synth/synth8/test4.vhdl

(limited to 'testsuite/synth/synth8/test4.vhdl')

diff --git a/testsuite/synth/synth8/test4.vhdl b/testsuite/synth/synth8/test4.vhdl
new file mode 100644
index 000000000..4875fa1ec
--- /dev/null
+++ b/testsuite/synth/synth8/test4.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test4 is
+  port (led: out std_logic_vector (7 downto 0);
+        rst : std_logic;
+        clk : std_logic);
+end test4;
+
+architecture synth of test4 is
+  signal int : std_logic_vector(1 downto 0);
+begin
+--  led(7) <= '0';
+--  led(6) <= '1';
+--  led(5) <= '0';
+--  led(3 downto 0) <= x"9";
+--  int(0) <= '0';
+  process (clk) is
+  begin
+    if rst = '1' then
+      int(1) <= '0';
+    elsif rising_edge (clk) then
+      int(1) <= not int(1);
+    end if;
+  end process;
+  led(5) <= int (1);
+--  led(4) <= int(0);
+end synth;
-- 
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