From 7678d2865436245e081a0a070a784d321442f513 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 8 Oct 2019 20:24:42 +0200
Subject: testsuite/syn: add testcase for #973

---
 testsuite/synth/issue973/ent.vhdl     | 16 ++++++++++++++++
 testsuite/synth/issue973/tb_ent.vhdl  | 22 ++++++++++++++++++++++
 testsuite/synth/issue973/testsuite.sh | 16 ++++++++++++++++
 3 files changed, 54 insertions(+)
 create mode 100644 testsuite/synth/issue973/ent.vhdl
 create mode 100644 testsuite/synth/issue973/tb_ent.vhdl
 create mode 100755 testsuite/synth/issue973/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue973/ent.vhdl b/testsuite/synth/issue973/ent.vhdl
new file mode 100644
index 000000000..796ab83ff
--- /dev/null
+++ b/testsuite/synth/issue973/ent.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+    port (
+        i : in std_logic_vector(7 downto 0);
+        o : out std_logic_vector(3 downto 0)
+    );
+end;
+
+architecture a of ent is
+    alias high_nibble : std_logic_vector(3 downto 0) is i(7 downto 4);
+begin
+    o <= high_nibble;
+end;
+
diff --git a/testsuite/synth/issue973/tb_ent.vhdl b/testsuite/synth/issue973/tb_ent.vhdl
new file mode 100644
index 000000000..328d48180
--- /dev/null
+++ b/testsuite/synth/issue973/tb_ent.vhdl
@@ -0,0 +1,22 @@
+entity tb_ent is
+end tb_ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent is
+  signal i : std_logic_vector (7 downto 0);
+  signal o : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.ent
+    port map (i, o);
+
+  process
+  begin
+    i <= x"b6";
+    wait for 1 ns;
+    assert o = x"b" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue973/testsuite.sh b/testsuite/synth/issue973/testsuite.sh
new file mode 100755
index 000000000..e30a741e0
--- /dev/null
+++ b/testsuite/synth/issue973/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in ent; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"
-- 
cgit v1.2.3