From 2918e833acf7f8652099cc290f465b79ad747df2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 6 Apr 2022 08:19:38 +0200
Subject: testsuite/synth: add tests for #2019

---
 testsuite/synth/issue2019/ent.vhdl     | 26 ++++++++++++++++++++++++++
 testsuite/synth/issue2019/repro1.vhdl  | 28 ++++++++++++++++++++++++++++
 testsuite/synth/issue2019/repro2.vhdl  | 13 +++++++++++++
 testsuite/synth/issue2019/testsuite.sh | 10 ++++++++++
 4 files changed, 77 insertions(+)
 create mode 100644 testsuite/synth/issue2019/ent.vhdl
 create mode 100644 testsuite/synth/issue2019/repro1.vhdl
 create mode 100644 testsuite/synth/issue2019/repro2.vhdl
 create mode 100755 testsuite/synth/issue2019/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/issue2019/ent.vhdl b/testsuite/synth/issue2019/ent.vhdl
new file mode 100644
index 000000000..fe4c17bf5
--- /dev/null
+++ b/testsuite/synth/issue2019/ent.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+  port (p : out std_ulogic_vector(3 downto 0));
+  type my_logic_vector is array (natural range <>) of std_ulogic;
+
+  function to_stdlogic (value : std_ulogic) return std_ulogic is
+  begin
+    return '0';
+  end function;
+
+  function to_stdlogic (value : my_logic_vector) return std_ulogic_vector is
+    variable tmp : std_ulogic_vector(value'range);
+  begin
+    tmp(0) := to_stdlogic(value(0));
+    --return tmp; -- uncommenting fixes it
+  end function;
+
+  signal s : my_logic_vector(3 downto 0);
+end entity;
+
+architecture a of ent is
+begin
+  p <= to_stdlogic(s);
+end architecture;
diff --git a/testsuite/synth/issue2019/repro1.vhdl b/testsuite/synth/issue2019/repro1.vhdl
new file mode 100644
index 000000000..fc66acb86
--- /dev/null
+++ b/testsuite/synth/issue2019/repro1.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+  port (p : out std_ulogic_vector(3 downto 0));
+end ent;
+
+
+architecture a of ent is
+  type my_logic_vector is array (natural range <>) of std_ulogic;
+
+  function to_stdlogic (value : std_ulogic) return std_ulogic is
+  begin
+    return '0';
+  end function;
+
+  function to_stdlogic (value : my_logic_vector) return std_ulogic_vector is
+    variable tmp : std_ulogic_vector(value'range);
+  begin
+    tmp(0) := to_stdlogic(value(0));
+    --return tmp; -- uncommenting fixes it
+  end function;
+
+  signal s : my_logic_vector(3 downto 0);
+
+begin
+  p <= to_stdlogic(s);
+end architecture;
diff --git a/testsuite/synth/issue2019/repro2.vhdl b/testsuite/synth/issue2019/repro2.vhdl
new file mode 100644
index 000000000..f2accf8fa
--- /dev/null
+++ b/testsuite/synth/issue2019/repro2.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro2 is
+  port (p : out std_ulogic_vector(3 downto 0));
+  signal s : std_ulogic_vector(3 downto 0);
+end entity;
+
+architecture a of repro2 is
+begin
+  s <= x"3";
+  p <= s;
+end architecture;
diff --git a/testsuite/synth/issue2019/testsuite.sh b/testsuite/synth/issue2019/testsuite.sh
new file mode 100755
index 000000000..743d05083
--- /dev/null
+++ b/testsuite/synth/issue2019/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only repro2
+
+synth_failure repro1.vhdl -e
+synth_failure ent.vhdl -e
+
+echo "Test successful"
-- 
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