From 299ff4d2291415af2a6457cf2f57de97f5a788e2 Mon Sep 17 00:00:00 2001
From: Ondrej Ille <ondrej.ille@gmail.com>
Date: Sat, 27 Mar 2021 10:56:02 +0100
Subject: testsuite: Add test for #1700

---
 testsuite/gna/issue1700/testsuite.sh | 10 +++++++++
 testsuite/gna/issue1700/top.vhd      | 39 ++++++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 testsuite/gna/issue1700/testsuite.sh
 create mode 100644 testsuite/gna/issue1700/top.vhd

(limited to 'testsuite')

diff --git a/testsuite/gna/issue1700/testsuite.sh b/testsuite/gna/issue1700/testsuite.sh
new file mode 100644
index 000000000..99bf4046d
--- /dev/null
+++ b/testsuite/gna/issue1700/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS='--std=08 -fpsl'
+analyze_failure top.vhd
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue1700/top.vhd b/testsuite/gna/issue1700/top.vhd
new file mode 100644
index 000000000..e641cc0c6
--- /dev/null
+++ b/testsuite/gna/issue1700/top.vhd
@@ -0,0 +1,39 @@
+
+Library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_top is
+end entity;
+
+
+architecture tb of tb_top is
+
+    signal a : std_logic;
+    signal clk_sys : std_logic;
+
+begin
+	
+    gen_clock_proc : process
+    begin
+        clk_sys <= '1';
+        wait for 5 ns;
+        clk_sys <= '0';
+        wait for 5 ns;
+    end process;
+	
+    test_proc : process
+    begin
+        wait until rising_edge(clk_sys);
+        wait until rising_edge(clk_sys);
+        wait until rising_edge(clk_sys);
+        wait until rising_edge(clk_sys);
+        std.env.finish;
+    end process;
+
+
+    --  psl default clock is rising_edge(clk_sys);
+
+    -- psl cov_simult_a_b_c : cover {a = '1'}[*3 to 2];
+
+end architecture tb;
+
-- 
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