From b9520bab77b8c1949c25fb5ca5bb55d739c8cfda Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 10 Nov 2018 07:34:24 +0100
Subject: Add testcase for #645.

Close #645
---
 testsuite/gna/issue645/foo.vhdl     | 33 +++++++++++++++++++++++++++++++++
 testsuite/gna/issue645/tb.vhdl      | 16 ++++++++++++++++
 testsuite/gna/issue645/testsuite.sh | 13 +++++++++++++
 3 files changed, 62 insertions(+)
 create mode 100644 testsuite/gna/issue645/foo.vhdl
 create mode 100644 testsuite/gna/issue645/tb.vhdl
 create mode 100755 testsuite/gna/issue645/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/issue645/foo.vhdl b/testsuite/gna/issue645/foo.vhdl
new file mode 100644
index 000000000..f04737d9e
--- /dev/null
+++ b/testsuite/gna/issue645/foo.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package types is
+  type t is array (natural range <>) of std_logic_vector; 
+  -- Warning : only compiles with --std=08
+end package;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.types.all;
+
+entity foo is
+  generic (n: natural; p: natural);
+  port (clk: in std_logic;
+        din: in std_logic_vector(p-1 downto 0);
+        dout: out t);
+end entity;
+
+architecture rtl of foo is
+  signal REG: t(0 to n-1)(p-1 downto 0); -- !!! CRASH HERE 
+begin
+  process (clk)
+  begin
+    if clk'event and clk='1' then
+      for i in 1 to n-1 loop
+        reg(i) <= reg(i-1);
+      end loop;			
+      reg(0) <= din;	    
+    end if;
+  end process;
+  dout <= reg;
+end architecture;
diff --git a/testsuite/gna/issue645/tb.vhdl b/testsuite/gna/issue645/tb.vhdl
new file mode 100644
index 000000000..cf0bf3128
--- /dev/null
+++ b/testsuite/gna/issue645/tb.vhdl
@@ -0,0 +1,16 @@
+entity tb is
+end tb;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.types.all;
+
+architecture behav of tb is
+  signal clk : std_logic;
+  signal l : std_logic_vector(31 downto 0);
+  signal res : t(3 downto 0)(31 downto 0);
+begin
+  dut : entity work.foo
+    generic map (n => 4, p => 32)
+    port map (clk, l, res);
+end behav;
diff --git a/testsuite/gna/issue645/testsuite.sh b/testsuite/gna/issue645/testsuite.sh
new file mode 100755
index 000000000..869613b87
--- /dev/null
+++ b/testsuite/gna/issue645/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+#exit 0
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze foo.vhdl
+analyze tb.vhdl
+elab_simulate tb
+
+clean
+
+echo "Test successful"
-- 
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