From cad4bda6a8c85c8103216324307206197152c417 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 19 Jan 2016 19:55:37 +0100
Subject: Add reproducer for bug24326.

---
 testsuite/gna/bug24326/repro1.vhdl     |  7 +++++++
 testsuite/gna/bug24326/tb_thingy7.vhdl | 27 +++++++++++++++++++++++++++
 testsuite/gna/bug24326/tb_thingy9.vhdl | 27 +++++++++++++++++++++++++++
 testsuite/gna/bug24326/testsuite.sh    | 11 +++++++++++
 4 files changed, 72 insertions(+)
 create mode 100644 testsuite/gna/bug24326/repro1.vhdl
 create mode 100644 testsuite/gna/bug24326/tb_thingy7.vhdl
 create mode 100644 testsuite/gna/bug24326/tb_thingy9.vhdl
 create mode 100755 testsuite/gna/bug24326/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/bug24326/repro1.vhdl b/testsuite/gna/bug24326/repro1.vhdl
new file mode 100644
index 000000000..624a7a7d8
--- /dev/null
+++ b/testsuite/gna/bug24326/repro1.vhdl
@@ -0,0 +1,7 @@
+entity repro1 is
+end;
+
+architecture behav of repro1 is
+  constant c : natural := 5 % 4;
+begin
+end;
diff --git a/testsuite/gna/bug24326/tb_thingy7.vhdl b/testsuite/gna/bug24326/tb_thingy7.vhdl
new file mode 100644
index 000000000..6df4205ca
--- /dev/null
+++ b/testsuite/gna/bug24326/tb_thingy7.vhdl
@@ -0,0 +1,27 @@
+entity tb_thingy is
+end tb_thingy;
+
+architecture tb of tb_thingy is
+	component thingy is
+		generic (
+			a_a : integer
+		);
+		port (
+			x_x : in bit;
+			y_y : out bit
+		);
+	end component;
+	signal stimuli : bit;
+	signal response : bit;
+begin
+
+	dut : thingy
+	generic map (
+		a_a => 42
+	)
+	port map (
+		x%x => stimuli, -- <==
+		y_y => response
+	);
+
+end tb;
diff --git a/testsuite/gna/bug24326/tb_thingy9.vhdl b/testsuite/gna/bug24326/tb_thingy9.vhdl
new file mode 100644
index 000000000..493b20d38
--- /dev/null
+++ b/testsuite/gna/bug24326/tb_thingy9.vhdl
@@ -0,0 +1,27 @@
+entity tb_thingy is
+end tb_thingy;
+
+architecture tb of tb_thingy is
+	component thingy is
+		generic (
+			a_a : integer
+		);
+		port (
+			x%x : in bit; -- <==
+			y_y : out bit
+		);
+	end component;
+	signal stimuli : bit;
+	signal response : bit;
+begin
+
+	dut : thingy
+	generic map (
+		a_a => 42
+	)
+	port map (
+		x_x => stimuli,
+		y_y => response
+	);
+
+end tb;
diff --git a/testsuite/gna/bug24326/testsuite.sh b/testsuite/gna/bug24326/testsuite.sh
new file mode 100755
index 000000000..a30c5a09b
--- /dev/null
+++ b/testsuite/gna/bug24326/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure tb_thingy7.vhdl
+analyze_failure tb_thingy9.vhdl
+analyze_failure repro1.vhdl
+
+clean
+
+echo "Test successful"
-- 
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