From d8ac5d6421e9156d3c9ebde905c838d7e277e181 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 14 Apr 2023 21:16:32 +0200 Subject: testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#183 --- testsuite/synth/synth183/test.vhdl | 45 +++++++++++++++++++++++++++++++++++ testsuite/synth/synth183/testsuite.sh | 11 +++++++++ 2 files changed, 56 insertions(+) create mode 100644 testsuite/synth/synth183/test.vhdl create mode 100755 testsuite/synth/synth183/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/synth/synth183/test.vhdl b/testsuite/synth/synth183/test.vhdl new file mode 100644 index 000000000..84fc93639 --- /dev/null +++ b/testsuite/synth/synth183/test.vhdl @@ -0,0 +1,45 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity test is + generic ( + BAUD_MULT : positive := 16 + ); + port ( + clk, rst : in std_logic; + + brk : out std_logic; + rx : in std_logic + ); +end test; + +architecture behavioral of test is + + signal rx_buf : std_logic := '1'; + signal break : std_logic := '0'; + +begin + + BREAK_DETECTOR: process (clk, rst) is + constant BREAK_CNT : positive := BAUD_MULT * 11; + variable count : natural range 0 to BREAK_CNT + 1 := 0; + begin + if (rising_edge(clk)) then + rx_buf <= rx; + -- Add to counter if '0', but halt count when break detected + count := (count + 1) when not(rx_buf or break); + -- Reset counter if '1' + count := 0 when rx_buf; + + break <= '0' when (count < BREAK_CNT) else '1'; + + if (rst = '1') then + count := 0; + break <= '0'; + end if; + end if; + end process; + + brk <= break; + +end behavioral; \ No newline at end of file diff --git a/testsuite/synth/synth183/testsuite.sh b/testsuite/synth/synth183/testsuite.sh new file mode 100755 index 000000000..eb1ca0714 --- /dev/null +++ b/testsuite/synth/synth183/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +synth_analyze test + +clean + +echo "Test successful" -- cgit v1.2.3