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ifneq ($(VERILOG_SOURCES),)

results.xml:
	@echo "Skipping simulation as Verilog is not supported on simulator=$(SIM)"
clean::

else

CMD_BIN := ghdl

ifdef GHDL_BIN_DIR
    CMD := $(shell which $(GHDL_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
else
    # auto-detect bin dir from system path
    CMD := $(shell which $(CMD_BIN) 2>/dev/null)
endif

ifeq (, $(CMD))
    $(error "Unable to locate command >$(CMD_BIN)<")
else
	GHDL_BIN_DIR := $(shell dirname $(CMD))
    export GHDL_BIN_DIR
endif

RTL_LIBRARY ?= work

ifdef VHDL_VERSION
	GHDL_STD = --std=$(VHDL_VERSION)
endif

.PHONY: analyse

# Compilation phase
analyse: $(VHDL_SOURCES) $(SIM_BUILD)
	cd $(SIM_BUILD); \
	$(CMD) -i $(GHDL_STD) --ieee=synopsys --mb-comments -fexplicit -frelaxed-rules --work=$(RTL_LIBRARY) -P$(UNISIM_DIR) $(VHDL_SOURCES); \
	$(CMD) -m $(GHDL_STD) $(ELABORATE_ARGS) --ieee=synopsys -frelaxed-rules --work=$(RTL_LIBRARY) -P$(UNISIM_DIR) $(TOPLEVEL)

results.xml: analyse  $(COCOTB_LIBS) $(COCOTB_VPI_LIB)
	cd $(SIM_BUILD); \
	PYTHONPATH=$(PYTHON_SIM_MODULES_PATH):$(LIB_DIR):$(SIM_ROOT):$(PWD):$(PYTHONPATH) LD_LIBRARY_PATH=$(GHDL_BIN_DIR)/../lib:$(LIB_DIR):$(LD_LIBRARY_PATH) MODULE=$(MODULE) \
        TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
	$(CMD) -r --ieee=synopsys -frelaxed-rules -P$(UNISIM_DIR) $(GHDL_STD) $(TOPLEVEL) --vpi=$(LIB_DIR)/libvpi.$(LIB_EXT) $(SIM_ARGS)

clean::
	-@rm -rf $(SIM_BUILD)
endif