-- Copyright (C) 2001-2002 The University of Cincinnati.  
-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

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-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
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-- ---------------------------------------------------------------------
--
-- $Id: test152.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
-- Cincinnati
----------------------------------------------------------------------
-- File          : test150.ams
-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created       : May 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- A simple RC  model...     
-- the test is done for checking the correct implementation of the simple
-- simultaneous equation statement with 'dot expression on RHS.  it checks
-- nature declaration, terminal and quantity declarations.  

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH ground reference;
    FUNCTION SIN(X : real) RETURN real;
    FUNCTION EXP(X : real) RETURN real;
END PACKAGE electricalSystem;
use work.electricalSystem.all;

entity test is
end entity;   

architecture atest of test is
terminal T1,T2:electrical;   
quantity V1 across I1 through T1 to T2;
quantity V2 across I2 through T2;
quantity VS across T1;

begin

e1:     V1 == I1*10.0; 
e2:     I2 == V2'dot*1.0e-12;

esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);

end architecture atest;