-- Copyright (C) 2000-2002 The University of Cincinnati.  
-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
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-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.

-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-- ---------------------------------------------------------------------
--
-- $Id: vccs.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH Ground reference;
    FUNCTION SIN(X : real) RETURN real;
    FUNCTION EXP(X : real) RETURN real;
    FUNCTION SQRT(X : real) RETURN real;
    FUNCTION POW(X,Y : real) RETURN real;
END PACKAGE electricalSystem;

use work.electricalsystem.all;

--entity declaration

ENTITY RLC IS

END RLC;

--architecture declaration

ARCHITECTURE behavior  OF RLC IS

constant R1: real :=20.0;
constant R2: real :=10.0;
constant R3: real :=5.0;
terminal T1,T2,T3:electrical;
quantity Vs1 across T1;
quantity Is1 through T2;
quantity Vr1 across Ir1 through T2 to T3;
quantity Vr2 across Ir2 through T3;

BEGIN 


res1 : vr1 == ir1 * r1;
res2 : vr2 == ir2 * r2;
res3 : is1 == vs1 * r3;
vsrc : vs1  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
                                * real(time'pos(now)) * 1.0e-15);
 
END architecture behavior;