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author | David Shah <davey1576@gmail.com> | 2018-01-13 15:55:32 +0000 |
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committer | David Shah <davey1576@gmail.com> | 2018-01-16 15:17:20 +0000 |
commit | a59472812c808416d2a56bccc07a9540357e18d9 (patch) | |
tree | c9052ba7174542a307b883190e3821cfe4d81d84 /icefuzz/Makefile | |
parent | 02a986b2f4b9d0cf5166a8a4915abe196116d259 (diff) | |
download | icestorm-a59472812c808416d2a56bccc07a9540357e18d9.tar.gz icestorm-a59472812c808416d2a56bccc07a9540357e18d9.tar.bz2 icestorm-a59472812c808416d2a56bccc07a9540357e18d9.zip |
Remove seperate 5k RAM DB and share with 8k instead
This should ensure that the 5k RAM routing entries are now complete,
fixing #115
Diffstat (limited to 'icefuzz/Makefile')
-rw-r--r-- | icefuzz/Makefile | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/icefuzz/Makefile b/icefuzz/Makefile index 0d9a8d9..12b7862 100644 --- a/icefuzz/Makefile +++ b/icefuzz/Makefile @@ -15,7 +15,7 @@ endif ifeq ($(DEVICECLASS), 5k) DEVICE := up5k-sg48 - RAM_SUFFIX := _5k + RAM_SUFFIX := _8k endif ifeq ($(DEVICECLASS), 8k) @@ -56,14 +56,11 @@ ifneq ($(RAM_SUFFIX),_8k) cp cached_ramt_8k.txt bitdata_ramt_8k.txt endif ifneq ($(RAM_SUFFIX),_5k) - cp cached_ramb_5k.txt bitdata_ramb_5k.txt - cp cached_ramt_5k.txt bitdata_ramt_5k.txt cp cached_dsp0_5k.txt bitdata_dsp0_5k.txt cp cached_dsp1_5k.txt bitdata_dsp1_5k.txt cp cached_dsp2_5k.txt bitdata_dsp2_5k.txt cp cached_dsp3_5k.txt bitdata_dsp3_5k.txt cp cached_ipcon_5k.txt bitdata_ipcon_5k.txt - endif ICEDEVICE=$(DEVICECLASS) python3 database.py python3 export.py |