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| -rw-r--r-- | docs/format.html | 34 | ||||
| -rw-r--r-- | docs/index.html | 39 | ||||
| -rw-r--r-- | docs/io_tile.html | 561 | ||||
| -rw-r--r-- | docs/logic_tile.html | 315 | ||||
| -rw-r--r-- | docs/ram_tile.html | 79 | ||||
| -rw-r--r-- | icebox/iceboxdb.py | 5 | ||||
| -rw-r--r-- | icefuzz/.gitignore | 1 | ||||
| -rw-r--r-- | icefuzz/Makefile | 22 | ||||
| -rw-r--r-- | icefuzz/cached_io.txt | 2 | ||||
| -rw-r--r-- | icefuzz/cached_ramb_8k.txt | 3 | ||||
| -rw-r--r-- | icefuzz/cached_ramt.txt | 3 | ||||
| -rw-r--r-- | icefuzz/database.py | 9 | ||||
| -rw-r--r-- | icefuzz/icecube.sh | 1 | ||||
| -rw-r--r-- | icefuzz/timings.py | 437 | ||||
| -rw-r--r-- | icefuzz/timings_1k.txt | 528 | ||||
| -rw-r--r-- | icefuzz/timings_8k.txt | 528 | ||||
| -rw-r--r-- | icefuzz/tmedges.ys | 20 | ||||
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| -rw-r--r-- | icefuzz/tmedges_8k.txt | 618 |
19 files changed, 3309 insertions, 508 deletions
diff --git a/docs/format.html b/docs/format.html index 75397e0..8c21c00 100644 --- a/docs/format.html +++ b/docs/format.html @@ -1,4 +1,18 @@ +<!DOCTYPE html> +<html><head><meta charset="UTF-8"> +<style> +.ctab { + margin-left: auto; + margin-right: auto; + border: 1px solid gray; +} +.ctab td, .ctab th { + padding: 3px; + border: 1px solid gray; +} +</style> <title>Project IceStorm – Bitstream File Format Documentation</title> +</head><body> <h1>Project IceStorm – Bitstream File Format Documentation</h1> <p> @@ -31,8 +45,7 @@ follows the command in case of the CRAM and BRAM commands. The following commands are known: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>Opcode</th><th>Description</th></tr> <tr><td>0</td><td>payload=0: CRAM Data<br/> payload=3: BRAM Data<br/> @@ -53,10 +66,9 @@ The following commands are known: payload=16: Enable cold boot<br/> payload=32: Enable warm boot</td></tr> </table> -</p> <p> -Use <tt>iceunpack -vv</tt> to display the commands as they are interpreted by the tool. +Use <span style="font-family:monospace">iceunpack -vv</span> to display the commands as they are interpreted by the tool. </p> <p> @@ -72,7 +84,7 @@ Most bytes in the bitstream are SRAM data bytes that should be written to the va in the FPGA. The following sequence is used to program an SRAM cell: </p> -<p><ul> +<ul> <li>Set bank width (opcode 6)</li> <li>Set bank height (opcode 7)</li> <li>Set bank offset (opcode 8)</li> @@ -80,7 +92,7 @@ in the FPGA. The following sequence is used to program an SRAM cell: <li>CRAM or BRAM Data Command</li> <li>(width * height / 8) data bytes</li> <li>two zero bytes</li> -</ul></p> +</ul> <p> The bank width and height parameters reflect the width and height of the SRAM bank. A large SRAM can @@ -104,7 +116,8 @@ The ordering of the data bits is in MSB first row-major order. <h2>Organization of the CRAM</h2> -<p><a href="checkerboard.png"><img style="float:right; padding:1em; padding-top:0" height="200" src="checkerboard.png" border="0"></a></p> +<p><a href="checkerboard.png"><img alt="Mapping of tile config bits to 2D CRAM" +style="float:right; padding:1em; padding-top:0; border:0" height="200" src="checkerboard.png"></a></p> <p> The chip is organized into four quadrants. Each CRAM memory bank contains the configuration bits for one quadrant. @@ -129,14 +142,14 @@ RAM tiles are 42 bits wide. (Notice the two slightly smaller columns for the RAM <p> The IO tiles on the top and bottom of the chip use a strange permutation pattern for their bits. It can be seen in the picture that their columns are spread out horizontally. What cannot be seen in the picture is the columns also are not in order and the bit -positions are vertically permuted as well. The <tt>CramIndexConverter</tt> class in <tt>icepack.cc</tt> encapsulates the calculations +positions are vertically permuted as well. The <span style="font-family:monospace">CramIndexConverter</span> class in <span style="font-family:monospace">icepack.cc</span> encapsulates the calculations that are neccessary to convert between tile-relative bit addresses and CRAM bank-relative bit addresses. </p> <p> The black pixels in the image correspond to CRAM bits that are not associated with any IO, LOGIC or RAM tile. -Some of them are unused, others are used by hard IPs or other global resources. The <tt>iceunpack</tt> tool reports -such bits, when set, with the "<tt>.extra_bit <i>bank x y</i></tt>" statement in the ASCII output format. +Some of them are unused, others are used by hard IPs or other global resources. The <span style="font-family:monospace">iceunpack</span> tool reports +such bits, when set, with the "<span style="font-family:monospace">.extra_bit <i>bank x y</i></span>" statement in the ASCII output format. </p> <h2>Organization of the BRAM</h2> @@ -152,3 +165,4 @@ The CRC is a 16 bit CRC. The (truncated) polynomial is 0x1021 (CRC-16-CCITT). Th the CRC to 0xFFFF. No zero padding is performed. </p> +</body></html> diff --git a/docs/index.html b/docs/index.html index 17b99a7..a400fef 100644 --- a/docs/index.html +++ b/docs/index.html @@ -1,4 +1,7 @@ +<!DOCTYPE html> +<html><head><meta charset="UTF-8"> <title>Project IceStorm</title> +</head><body> <h1>Project IceStorm</h1> <p> @@ -102,16 +105,16 @@ after updating your IceStorm installation. <h3>IcePack/IceUnpack</h3> <p> -The <tt>iceunpack</tt> program converts an iCE40 <tt>.bin</tt> file into the IceBox ASCII format -that has blocks of <tt>0</tt> and <tt>1</tt> for the config bits for each tile in the chip. The -<tt>icepack</tt> program converts such an ASCII file back to an iCE40 <tt>.bin</tt> file. +The <span style="font-family:monospace">iceunpack</span> program converts an iCE40 <span style="font-family:monospace">.bin</span> file into the IceBox ASCII format +that has blocks of <span style="font-family:monospace">0</span> and <span style="font-family:monospace">1</span> for the config bits for each tile in the chip. The +<span style="font-family:monospace">icepack</span> program converts such an ASCII file back to an iCE40 <span style="font-family:monospace">.bin</span> file. </p> <h3>IceBox</h3> <p> A python library and various tools for working with IceBox ASCII files and accessing -the device database. For example <tt>icebox_vlog</tt> converts our ASCII file +the device database. For example <span style="font-family:monospace">icebox_vlog</span> converts our ASCII file dump of a bitstream into a Verilog file that implements an equivalent circuit. </p> @@ -130,7 +133,7 @@ A tool for packing multiple bitstream files into one iCE40 multiboot image file. <h3>ChipDB</h3> <p> -The IceStorm Makefile builds and installs two files: <tt>chipdb-1k.txt</tt> and <tt>chipdb-8k.txt</tt>. +The IceStorm Makefile builds and installs two files: <span style="font-family:monospace">chipdb-1k.txt</span> and <span style="font-family:monospace">chipdb-8k.txt</span>. This files contain all the relevant information for arachne-pnr to place&route a design and create an IceBox ASCII file for the placed and routed design. </p> @@ -163,8 +166,8 @@ The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles. </ul> <p> -The <tt>iceunpack</tt> program can be used to convert the bitstream into an ASCII file -that has a block of <tt>0</tt> and <tt>1</tt> characters for each tile. For example: +The <span style="font-family:monospace">iceunpack</span> program can be used to convert the bitstream into an ASCII file +that has a block of <span style="font-family:monospace">0</span> and <span style="font-family:monospace">1</span> characters for each tile. For example: </p> <pre style="padding-left: 3em">.logic_tile 12 12 @@ -186,12 +189,12 @@ that has a block of <tt>0</tt> and <tt>1</tt> characters for each tile. For exam 000000000000000000000000000101010000101010100000000000</pre> <p> -This bits are referred to as <tt>B<i>y</i>[<i>x</i>]</tt> in the documentation. For example, <tt>B0</tt> is the first -line, <tt>B0[0]</tt> the first bit in the first line, and <tt>B15[53]</tt> the last bit in the last line. +This bits are referred to as <span style="font-family:monospace">B<i>y</i>[<i>x</i>]</span> in the documentation. For example, <span style="font-family:monospace">B0</span> is the first +line, <span style="font-family:monospace">B0[0]</span> the first bit in the first line, and <span style="font-family:monospace">B15[53]</span> the last bit in the last line. </p> <p> -The <tt>icebox_explain</tt> program can be used to turn this block of config bits into a description of the cell +The <span style="font-family:monospace">icebox_explain</span> program can be used to turn this block of config bits into a description of the cell configuration: </p> @@ -205,16 +208,16 @@ buffer sp12_h_r_20 local_g1_4</pre> <p> IceBox contains a database of the wires and configuration bits that can be found in iCE40 tiles. This database can be accessed via the IceBox Python API. But IceBox is a large hack. So it is recommended to only use the IceBox API -to export this database into a format that fits the target application. See <tt>icebox_chipdb</tt> for +to export this database into a format that fits the target application. See <span style="font-family:monospace">icebox_chipdb</span> for an example program that does that. </p> <p> The recommended approach for learning how to use this documentation is to synthesize very simple circuits using Yosys and Arachne-pnr, run the icestorm -tool <tt>icebox_explain</tt> on the resulting bitstream files, and analyze the +tool <span style="font-family:monospace">icebox_explain</span> on the resulting bitstream files, and analyze the results using the HTML export of the database mentioned above. -<tt>icebox_vlog</tt> can be used to convert the bitstream to Verilog. The +<span style="font-family:monospace">icebox_vlog</span> can be used to convert the bitstream to Verilog. The output file of this tool will also outline the signal paths in comments added to the generated Verilog code. </p> @@ -243,7 +246,7 @@ $ icepack example.txt example.bin </pre> <p> -We would get something like the following <tt>icebox_explain</tt> output: +We would get something like the following <span style="font-family:monospace">icebox_explain</span> output: </p> <pre style="padding-left: 3em">$ icebox_explain example.txt @@ -280,7 +283,7 @@ buffer neigh_op_lft_0 local_g0_0 buffer sp4_h_r_24 local_g3_0</pre> <p> -And something like the following <tt>icebox_vlog</tt> output: +And something like the following <span style="font-family:monospace">icebox_vlog</span> output: </p> <pre style="padding-left: 3em">$ icebox_vlog -p example.pcf example.txt @@ -353,9 +356,7 @@ Links to related projects. Contact me at clifford@clifford.at if you have an int <li><a href="https://hackaday.io/project/6636-iced-an-arduino-style-board-with-ice-fpga">ICEd = an Arduino Style Board, with ICE FPGA</a> </ul> -<p> <hr> -</p> <p> In papers and reports, please refer to Project IceStorm as follows: Clifford Wolf, Mathias Lasser. Project IceStorm. http://www.clifford.at/icestorm/, @@ -368,11 +369,11 @@ e.g. using the following BibTeX code: howpublished = "\url{http://www.clifford.at/icestorm/}" }</pre> -<p> <hr> -</p> <p> <i>Documentation mostly by Clifford Wolf <clifford@clifford.at> in 2015. Based on research by Mathias Lasser and Clifford Wolf.<br/> Buy an <a href="http://www.latticesemi.com/icestick">iCEstick</a> from Lattice and see what you can do with the information provided here. Buy a few because you might break some..</i> </p> + +</body></html> diff --git a/docs/io_tile.html b/docs/io_tile.html index 6adc683..1a5ca61 100644 --- a/docs/io_tile.html +++ b/docs/io_tile.html @@ -1,4 +1,27 @@ +<!DOCTYPE html> +<html><head><meta charset="UTF-8"> +<style> +.xtab { + margin-left: auto; + margin-right: auto; +} +.xtab td, .xtab th { + padding: 10px; + vertical-align: top; +} +.ctab { + margin-left: auto; + margin-right: auto; + border: 1px solid gray; +} +.ctab td, .ctab th { + padding: 3px; + border: 1px solid gray; + vertical-align: baseline; +} +</style> <title>Project IceStorm – IO Tile Documentation</title> +</head><body> <h1>Project IceStorm – IO Tile Documentation</h1> <p> @@ -9,31 +32,31 @@ This is work in progress.</i> <h2>Span-4 and Span-12 Wires</h2> -<p><a href="iosp.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="iosp.svg" border="0"></a></p> +<p><a href="iosp.svg"><img alt="IO Tile Span-Wires" style="float:right; padding:1em; padding-top:0; border:0" height="200" src="iosp.svg"></a></p> <p> The image on the right shows the span-wires of a left (or right) io cell (click to enlarge). </p> <p> -A left/right io cell has 16 connections named <tt>span4_vert_t_0</tt> to <tt>span4_vert_t_15</tt> on its top edge and -16 connections named <tt>span4_vert_b_0</tt> to <tt>span4_vert_b_15</tt> on its bottom edge. The nets <tt>span4_vert_t_0</tt> -to <tt>span4_vert_t_11</tt> are connected to <tt>span4_vert_b_4</tt> to <tt>span4_vert_b_15</tt>. The span-4 and span-12 wires -of the adjacent logic cell are connected to the nets <tt>span4_horz_0</tt> to <tt>span4_horz_47</tt> and <tt>span12_horz_0</tt> -to <tt>span12_horz_23</tt>. +A left/right io cell has 16 connections named <span style="font-family:monospace">span4_vert_t_0</span> to <span style="font-family:monospace">span4_vert_t_15</span> on its top edge and +16 connections named <span style="font-family:monospace">span4_vert_b_0</span> to <span style="font-family:monospace">span4_vert_b_15</span> on its bottom edge. The nets <span style="font-family:monospace">span4_vert_t_0</span> +to <span style="font-family:monospace">span4_vert_t_11</span> are connected to <span style="font-family:monospace">span4_vert_b_4</span> to <span style="font-family:monospace">span4_vert_b_15</span>. The span-4 and span-12 wires +of the adjacent logic cell are connected to the nets <span style="font-family:monospace">span4_horz_0</span> to <span style="font-family:monospace">span4_horz_47</span> and <span style="font-family:monospace">span12_horz_0</span> +to <span style="font-family:monospace">span12_horz_23</span>. </p> <p> -A top/bottom io cell has 16 connections named <tt>span4_vert_l_0</tt> to <tt>span4_vert_l_15</tt> on its top edge and -16 connections named <tt>span4_vert_r_0</tt> to <tt>span4_vert_r_15</tt> on its bottom edge. The nets <tt>span4_vert_l_0</tt> -to <tt>span4_vert_l_11</tt> are connected to <tt>span4_vert_r_4</tt> to <tt>span4_vert_r_15</tt>. The span-4 and span-12 wires -of the adjacent logic cell are connected to the nets <tt>span4_vert_0</tt> to <tt>span4_vert_47</tt> and <tt>span12_vert_0</tt> -to <tt>span12_vert_23</tt>. +A top/bottom io cell has 16 connections named <span style="font-family:monospace">span4_vert_l_0</span> to <span style="font-family:monospace">span4_vert_l_15</span> on its top edge and +16 connections named <span style="font-family:monospace">span4_vert_r_0</span> to <span style="font-family:monospace">span4_vert_r_15</span> on its bottom edge. The nets <span style="font-family:monospace">span4_vert_l_0</span> +to <span style="font-family:monospace">span4_vert_l_11</span> are connected to <span style="font-family:monospace">span4_vert_r_4</span> to <span style="font-family:monospace">span4_vert_r_15</span>. The span-4 and span-12 wires +of the adjacent logic cell are connected to the nets <span style="font-family:monospace">span4_vert_0</span> to <span style="font-family:monospace">span4_vert_47</span> and <span style="font-family:monospace">span12_vert_0</span> +to <span style="font-family:monospace">span12_vert_23</span>. </p> <p> The vertical span4 wires of left/right io cells are connected "around the corner" to the horizontal span4 wires of the top/bottom -io cells. For example <tt>span4_vert_b_0</tt> of IO cell (0 1) is connected to <tt>span4_horz_l_0</tt> (<tt>span4_horz_r_4</tt>) +io cells. For example <span style="font-family:monospace">span4_vert_b_0</span> of IO cell (0 1) is connected to <span style="font-family:monospace">span4_horz_l_0</span> (<span style="font-family:monospace">span4_horz_r_4</span>) of IO cell (1 0). </p> @@ -45,26 +68,24 @@ connecting IO tiles to each other are not pairwise crossed out. <h2>IO Blocks</h2> <p> -Each IO tile contains two IO blocks. Each IO block essentially implements the <tt>SB_IO</tt> +Each IO tile contains two IO blocks. Each IO block essentially implements the <span style="font-family:monospace">SB_IO</span> primitive from the Lattice iCE Technology Library. Some inputs are shared between the two IO blocks. The following table lists how the -wires in the logic tile map to the <tt>SB_IO</tt> primitive ports: +wires in the logic tile map to the <span style="font-family:monospace">SB_IO</span> primitive ports: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>SB_IO Port</th><th>IO Block 0</th><th>IO Block 1</th></tr> -<tr><td>D_IN_0</td><td><tt>io_0/D_IN_0</tt></td><td><tt>io_1/D_IN_0</tt></td></tr> -<tr><td>D_IN_1</td><td><tt>io_0/D_IN_1</tt></td><td><tt>io_1/D_IN_1</tt></td></tr> -<tr><td>D_OUT_0</td><td><tt>io_0/D_OUT_0</tt></td><td><tt>io_1/D_OUT_0</tt></td></tr> -<tr><td>D_OUT_1</td><td><tt>io_0/D_OUT_1</tt></td><td><tt>io_1/D_OUT_1</tt></td></tr> -<tr><td>OUTPUT_ENABLE</td><td><tt>io_0/OUT_ENB</tt></td><td><tt>io_1/OUT_ENB</tt></td></tr> -<tr><td>CLOCK_ENABLE</td><td colspan="2"><tt>io_global/cen</tt></td></tr> -<tr><td>INPUT_CLK</td><td colspan="2"><tt>io_global/inclk</tt></td></tr> -<tr><td>OUTPUT_CLK</td><td colspan="2"><tt>io_global/outclk</tt></td></tr> -<tr><td>LATCH_INPUT_VALUE</td><td colspan="2"><tt>io_global/latch</tt></td></tr> +<tr><td>D_IN_0</td><td><span style="font-family:monospace">io_0/D_IN_0</span></td><td><span style="font-family:monospace">io_1/D_IN_0</span></td></tr> +<tr><td>D_IN_1</td><td><span style="font-family:monospace">io_0/D_IN_1</span></td><td><span style="font-family:monospace">io_1/D_IN_1</span></td></tr> +<tr><td>D_OUT_0</td><td><span style="font-family:monospace">io_0/D_OUT_0</span></td><td><span style="font-family:monospace">io_1/D_OUT_0</span></td></tr> +<tr><td>D_OUT_1</td><td><span style="font-family:monospace">io_0/D_OUT_1</span></td><td><span style="font-family:monospace">io_1/D_OUT_1</span></td></tr> +<tr><td>OUTPUT_ENABLE</td><td><span style="font-family:monospace">io_0/OUT_ENB</span></td><td><span style="font-family:monospace">io_1/OUT_ENB</span></td></tr> +<tr><td>CLOCK_ENABLE</td><td colspan="2"><span style="font-family:monospace">io_global/cen</span></td></tr> +<tr><td>INPUT_CLK</td><td colspan="2"><span style="font-family:monospace">io_global/inclk</span></td></tr> +<tr><td>OUTPUT_CLK</td><td colspan="2"><span style="font-family:monospace">io_global/outclk</span></td></tr> +<tr><td>LATCH_INPUT_VALUE</td><td colspan="2"><span style="font-family:monospace">io_global/latch</span></td></tr> </table> -</p> <p> Like the inputs to logic cells, the inputs to IO blocks are routed to the IO block via a two-stage process. A signal @@ -72,36 +93,34 @@ is first routed to one of 16 local tracks in the IO tile and then from the local </p> <p> -The <tt>io_global/latch</tt> signal is shared among all IO tiles on an edge of the chip and is driven by <tt>fabout</tt> -from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the <tt>io_global/latch</tt> signal are: +The <span style="font-family:monospace">io_global/latch</span> signal is shared among all IO tiles on an edge of the chip and is driven by <span style="font-family:monospace">fabout</span> +from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the <span style="font-family:monospace">io_global/latch</span> signal are: (0, 7), (13, 10), (5, 0), and (8, 17) </p> <p> -A logic tile sends the output of its eight logic cells to its neighbour tiles. An IO tile does the same thing with the four <tt>D_IN</tt> -signals created by its two IO blocks. The <tt>D_IN</tt> signals map to logic function indices as follows: +A logic tile sends the output of its eight logic cells to its neighbour tiles. An IO tile does the same thing with the four <span style="font-family:monospace">D_IN</span> +signals created by its two IO blocks. The <span style="font-family:monospace">D_IN</span> signals map to logic function indices as follows: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>Function Index</th><th>D_IN Wire</th></tr> -<tr><td>0</td><td><tt>io_0/D_IN_0</tt></td></tr> -<tr><td>1</td><td><tt>io_0/D_IN_1</tt></td></tr> -<tr><td>2</td><td><tt>io_1/D_IN_0</tt></td></tr> -<tr><td>3</td><td><tt>io_1/D_IN_1</tt></td></tr> -<tr><td>4</td><td><tt>io_0/D_IN_0</tt></td></tr> -<tr><td>5</td><td><tt>io_0/D_IN_1</tt></td></tr> -<tr><td>6</td><td><tt>io_1/D_IN_0</tt></td></tr> -<tr><td>7</td><td><tt>io_1/D_IN_1</tt></td></tr> +<tr><td>0</td><td><span style="font-family:monospace">io_0/D_IN_0</span></td></tr> +<tr><td>1</td><td><span style="font-family:monospace">io_0/D_IN_1</span></td></tr> +<tr><td>2</td><td><span style="font-family:monospace">io_1/D_IN_0</span></td></tr> +<tr><td>3</td><td><span style="font-family:monospace">io_1/D_IN_1</span></td></tr> +<tr><td>4</td><td><span style="font-family:monospace">io_0/D_IN_0</span></td></tr> +<tr><td>5</td><td><span style="font-family:monospace">io_0/D_IN_1</span></td></tr> +<tr><td>6</td><td><span style="font-family:monospace">io_1/D_IN_0</span></td></tr> +<tr><td>7</td><td><span style="font-family:monospace">io_1/D_IN_1</span></td></tr> </table> -</p> <p> -For example the signal <tt>io_1/D_IN_0</tt> in IO tile (0, 5) can be seen as <tt>neigh_op_lft_2</tt> and <tt>neigh_op_lft_6</tt> in LOGIC tile (1, 5). +For example the signal <span style="font-family:monospace">io_1/D_IN_0</span> in IO tile (0, 5) can be seen as <span style="font-family:monospace">neigh_op_lft_2</span> and <span style="font-family:monospace">neigh_op_lft_6</span> in LOGIC tile (1, 5). </p> <p> -Each IO Tile has 2 <tt>NegClk</tt> configuration bits, suggesting that the +Each IO Tile has 2 <span style="font-family:monospace">NegClk</span> configuration bits, suggesting that the clock signals can be inverted independently for the the two IO blocks in the tile. However, the Lattice tools refuse to pack two IO blocks with different clock polarity into the same IO tile. In our tests we only managed to either set or clear @@ -109,159 +128,157 @@ both NegClk bits. </p> <p> -Each IO block has two <tt>IoCtrl IE</tt> bits that enable the input buffers and -two <tt>IoCtrl REN</tt> bits that enable the pull up resistors. Both bits are active +Each IO block has two <span style="font-family:monospace">IoCtrl IE</span> bits that enable the input buffers and +two <span style="font-family:monospace">IoCtrl REN</span> bits that enable the pull up resistors. Both bits are active low, i.e. an unused IO tile will have both IE bits set and both REN bits cleared (the default behavior is to enable pullup resistors on all unused pins). Note that -<tt>icebox_explain.py</tt> will ignore all IO tiles that only have the two <tt>IoCtrl -IE</tt> bits set. +<span style="font-family:monospace">icebox_explain.py</span> will ignore all IO tiles that only have the two <span style="font-family:monospace">IoCtrl +IE</span> bits set. </p> <p> -However, the <tt>IoCtrl IE_0/IE_1</tt> and <tt>IoCtrl REN_0/REN_1</tt> do not +However, the <span style="font-family:monospace">IoCtrl IE_0/IE_1</span> and <span style="font-family:monospace">IoCtrl REN_0/REN_1</span> do not necessarily configure the IO PIN that are connected to the IO block in the same tile, and if they do the numbers (0/1) do not necessarily match. As a general rule, the pins on the right and bottom side of the chips match up with the IO blocks and for the pins on the left and top side the numbers must be swapped. But in some cases the IO block -and the set of <tt>IE/REN</tt> are not even located in the same tile. The following -table lists the correlation between IO blocks and <tt>IE/REN</tt> bits for the +and the set of <span style="font-family:monospace">IE/REN</span> are not even located in the same tile. The following +table lists the correlation between IO blocks and <span style="font-family:monospace">IE/REN</span> bits for the 1K chip: </p> -<p align="center"> -<table cellpadding="10"> -<tr><td valign="top"> +<table class="xtab"> +<tr><td> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>IO Block</th><th>IE/REN Block</th></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 14 1</td><td align="center">0 14 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 14 0</td><td align="center">0 14 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 13 1</td><td align="center">0 13 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 13 0</td><td align="center">0 13 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 12 1</td><td align="center">0 12 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 12 0</td><td align="center">0 12 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 11 1</td><td align="center">0 11 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 11 0</td><td align="center">0 11 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 10 1</td><td align="center">0 10 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 10 0</td><td align="center">0 10 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 9 1</td><td align="center">0 9 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 9 0</td><td align="center">0 9 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 8 1</td><td align="center">0 8 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 8 0</td><td align="center">0 8 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 6 1</td><td align="center">0 6 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 6 0</td><td align="center">0 6 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 5 1</td><td align="center">0 5 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 5 0</td><td align="center">0 5 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 4 1</td><td align="center">0 4 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 4 0</td><td align="center">0 4 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 3 1</td><td align="center">0 3 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 3 0</td><td align="center">0 3 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 2 1</td><td align="center">0 2 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0 2 0</td><td align="center">0 2 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 14 1</td><td style="text-align:center">0 14 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 14 0</td><td style="text-align:center">0 14 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 13 1</td><td style="text-align:center">0 13 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 13 0</td><td style="text-align:center">0 13 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 12 1</td><td style="text-align:center">0 12 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 12 0</td><td style="text-align:center">0 12 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 11 1</td><td style="text-align:center">0 11 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 11 0</td><td style="text-align:center">0 11 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 10 1</td><td style="text-align:center">0 10 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 10 0</td><td style="text-align:center">0 10 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 9 1</td><td style="text-align:center">0 9 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 9 0</td><td style="text-align:center">0 9 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 8 1</td><td style="text-align:center">0 8 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 8 0</td><td style="text-align:center">0 8 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 6 1</td><td style="text-align:center">0 6 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 6 0</td><td style="text-align:center">0 6 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 5 1</td><td style="text-align:center">0 5 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 5 0</td><td style="text-align:center">0 5 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 4 1</td><td style="text-align:center">0 4 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 4 0</td><td style="text-align:center">0 4 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 3 1</td><td style="text-align:center">0 3 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 3 0</td><td style="text-align:center">0 3 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 2 1</td><td style="text-align:center">0 2 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 2 0</td><td style="text-align:center">0 2 1</td></tr> </table> -</td><td valign="top"> +</td><td> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>IO Block</th><th>IE/REN Block</th></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 0 0</td><td align="center"> 1 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 0 1</td><td align="center"> 1 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 0 0</td><td align="center"> 2 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 0 1</td><td align="center"> 2 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 0 0</td><td align="center"> 3 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 0 1</td><td align="center"> 3 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 0 0</td><td align="center"> 4 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 0 1</td><td align="center"> 4 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 0 0</td><td align="center"> 5 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 0 1</td><td align="center"> 5 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 0 1</td><td align="center"> 6 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 0 0</td><td align="center"> 6 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 0 0</td><td align="center"> 7 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 0 1</td><td align="center"> 7 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 0 0</td><td align="center"> 8 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 0 1</td><td align="center"> 8 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 0 0</td><td align="center"> 9 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 0 1</td><td align="center"> 9 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">10 0 0</td><td align="center">10 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">10 0 1</td><td align="center">10 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">11 0 0</td><td align="center">11 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">11 0 1</td><td align="center">11 0 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">12 0 0</td><td align="center">12 0 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">12 0 1</td><td align="center">12 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 1 0 0</td><td style="text-align:center"> 1 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 1 0 1</td><td style="text-align:center"> 1 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 2 0 0</td><td style="text-align:center"> 2 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 2 0 1</td><td style="text-align:center"> 2 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 3 0 0</td><td style="text-align:center"> 3 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 3 0 1</td><td style="text-align:center"> 3 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 4 0 0</td><td style="text-align:center"> 4 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 4 0 1</td><td style="text-align:center"> 4 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 5 0 0</td><td style="text-align:center"> 5 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 5 0 1</td><td style="text-align:center"> 5 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 6 0 1</td><td style="text-align:center"> 6 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 7 0 0</td><td style="text-align:center"> 6 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 6 0 0</td><td style="text-align:center"> 7 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 7 0 1</td><td style="text-align:center"> 7 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 8 0 0</td><td style="text-align:center"> 8 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 8 0 1</td><td style="text-align:center"> 8 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 9 0 0</td><td style="text-align:center"> 9 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 9 0 1</td><td style="text-align:center"> 9 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">10 0 0</td><td style="text-align:center">10 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">10 0 1</td><td style="text-align:center">10 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">11 0 0</td><td style="text-align:center">11 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">11 0 1</td><td style="text-align:center">11 0 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">12 0 0</td><td style="text-align:center">12 0 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">12 0 1</td><td style="text-align:center">12 0 1</td></tr> </table> -</td><td valign="top"> +</td><td> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>IO Block</th><th>IE/REN Block</th></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 1 0</td><td align="center">13 1 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 1 1</td><td align="center">13 1 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 2 0</td><td align="center">13 2 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 2 1</td><td align="center">13 2 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 3 1</td><td align="center">13 3 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 4 0</td><td align="center">13 4 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 4 1</td><td align="center">13 4 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 6 0</td><td align="center">13 6 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 6 1</td><td align="center">13 6 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 7 0</td><td align="center">13 7 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 7 1</td><td align="center">13 7 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 8 0</td><td align="center">13 8 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 8 1</td><td align="center">13 8 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 9 0</td><td align="center">13 9 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 9 1</td><td align="center">13 9 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 11 0</td><td align="center">13 10 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 11 1</td><td align="center">13 10 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 12 0</td><td align="center">13 11 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 12 1</td><td align="center">13 11 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 13 0</td><td align="center">13 13 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 13 1</td><td align="center">13 13 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 14 0</td><td align="center">13 14 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 14 1</td><td align="center">13 14 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 15 0</td><td align="center">13 15 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">13 15 1</td><td align="center">13 15 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 1 0</td><td style="text-align:center">13 1 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 1 1</td><td style="text-align:center">13 1 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 2 0</td><td style="text-align:center">13 2 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 2 1</td><td style="text-align:center">13 2 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 3 1</td><td style="text-align:center">13 3 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 4 0</td><td style="text-align:center">13 4 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 4 1</td><td style="text-align:center">13 4 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 6 0</td><td style="text-align:center">13 6 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 6 1</td><td style="text-align:center">13 6 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 7 0</td><td style="text-align:center">13 7 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 7 1</td><td style="text-align:center">13 7 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 8 0</td><td style="text-align:center">13 8 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 8 1</td><td style="text-align:center">13 8 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 9 0</td><td style="text-align:center">13 9 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 9 1</td><td style="text-align:center">13 9 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 11 0</td><td style="text-align:center">13 10 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 11 1</td><td style="text-align:center">13 10 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 12 0</td><td style="text-align:center">13 11 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 12 1</td><td style="text-align:center">13 11 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 13 0</td><td style="text-align:center">13 13 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 13 1</td><td style="text-align:center">13 13 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 14 0</td><td style="text-align:center">13 14 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 14 1</td><td style="text-align:center">13 14 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 15 0</td><td style="text-align:center">13 15 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 15 1</td><td style="text-align:center">13 15 1</td></tr> </table> -</td><td valign="top"> +</td><td> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>IO Block</th><th>IE/REN Block</th></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">12 17 1</td><td align="center">12 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">12 17 0</td><td align="center">12 17 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">11 17 1</td><td align="center">11 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">11 17 0</td><td align="center">11 17 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">10 17 1</td><td align="center"> 9 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">10 17 0</td><td align="center"> 9 17 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 17 1</td><td align="center">10 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 17 0</td><td align="center">10 17 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 17 1</td><td align="center"> 8 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 17 0</td><td align="center"> 8 17 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 17 1</td><td align="center"> 7 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 17 0</td><td align="center"> 7 17 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 17 1</td><td align="center"> 6 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 17 1</td><td align="center"> 5 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 17 0</td><td align="center"> 5 17 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 17 1</td><td align="center"> 4 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 17 0</td><td align="center"> 4 17 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 17 1</td><td align="center"> 3 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 17 0</td><td align="center"> 3 17 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 17 1</td><td align="center"> 2 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 17 0</td><td align="center"> 2 17 0</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 17 1</td><td align="center"> 1 17 1</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 17 0</td><td align="center"> 1 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">12 17 1</td><td style="text-align:center">12 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">12 17 0</td><td style="text-align:center">12 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">11 17 1</td><td style="text-align:center">11 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">11 17 0</td><td style="text-align:center">11 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">10 17 1</td><td style="text-align:center"> 9 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">10 17 0</td><td style="text-align:center"> 9 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 9 17 1</td><td style="text-align:center">10 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 9 17 0</td><td style="text-align:center">10 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 8 17 1</td><td style="text-align:center"> 8 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 8 17 0</td><td style="text-align:center"> 8 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 7 17 1</td><td style="text-align:center"> 7 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 7 17 0</td><td style="text-align:center"> 7 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 6 17 1</td><td style="text-align:center"> 6 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 5 17 1</td><td style="text-align:center"> 5 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 5 17 0</td><td style="text-align:center"> 5 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 4 17 1</td><td style="text-align:center"> 4 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 4 17 0</td><td style="text-align:center"> 4 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 3 17 1</td><td style="text-align:center"> 3 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 3 17 0</td><td style="text-align:center"> 3 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 2 17 1</td><td style="text-align:center"> 2 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 2 17 0</td><td style="text-align:center"> 2 17 0</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 1 17 1</td><td style="text-align:center"> 1 17 1</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 1 17 0</td><td style="text-align:center"> 1 17 0</td></tr> </table> </table> -</p> <p> When an input pin pair is used as LVDS pair (IO standard -<tt>SB_LVDS_INPUT</tt>, bank 3 / left edge only), then the four bits -<tt>IoCtrl IE_0/IE_1</tt> and <tt>IoCtrl REN_0/REN_1</tt> are all set, as well -as the <tt>IoCtrl LVDS</tt> bit. +<span style="font-family:monospace">SB_LVDS_INPUT</span>, bank 3 / left edge only), then the four bits +<span style="font-family:monospace">IoCtrl IE_0/IE_1</span> and <span style="font-family:monospace">IoCtrl REN_0/REN_1</span> are all set, as well +as the <span style="font-family:monospace">IoCtrl LVDS</span> bit. </p> <p> -In the iCE 8k devices the <tt>IoCtrl IE</tt> bits are active high. So an unused +In the iCE 8k devices the <span style="font-family:monospace">IoCtrl IE</span> bits are active high. So an unused IO tile on an 8k chip has all bits cleared. </p> @@ -276,55 +293,51 @@ tile are used. In IceBox nomenclature such bits are called "extra bits". <p> The following table lists which pins / IO blocks may be used to drive -which global net, and what <tt>.extra</tt> statements in the IceBox ASCII file +which global net, and what <span style="font-family:monospace">.extra</span> statements in the IceBox ASCII file format to represent the corresponding configuration bits: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>Glb Net</th><th>Pin<br/>(HX1K-TQ144)</th><th>IO Tile +<br/>Block #</th><th>IceBox Statement</th></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">0</td><td align="center"> 93</td><td align="center">13 8 1</td><td align="center">.extra_bit 0 330 142</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">1</td><td align="center"> 21</td><td align="center"> 0 8 1</td><td align="center">.extra_bit 0 331 142</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">2</td><td align="center">128</td><td align="center"> 7 17 0</td><td align="center">.extra_bit 1 330 143</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">3</td><td align="center"> 50</td><td align="center"> 7 0 0</td><td align="center">.extra_bit 1 331 143</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">4</td><td align="center"> 20</td><td align="center"> 0 9 0</td><td align="center">.extra_bit 1 330 142</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">5</td><td align="center"> 94</td><td align="center">13 9 0</td><td align="center">.extra_bit 1 331 142</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">6</td><td align="center"> 49</td><td align="center"> 6 0 1</td><td align="center">.extra_bit 0 330 143</td></tr> -<tr style="white-space: pre; font-family: monospace"><td align="center">7</td><td align="center">129</td><td align="center"> 6 17 1</td><td align="center">.extra_bit 0 331 143</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0</td><td style="text-align:center"> 93</td><td style="text-align:center">13 8 1</td><td style="text-align:center">.extra_bit 0 330 142</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">1</td><td style="text-align:center"> 21</td><td style="text-align:center"> 0 8 1</td><td style="text-align:center">.extra_bit 0 331 142</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">2</td><td style="text-align:center">128</td><td style="text-align:center"> 7 17 0</td><td style="text-align:center">.extra_bit 1 330 143</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">3</td><td style="text-align:center"> 50</td><td style="text-align:center"> 7 0 0</td><td style="text-align:center">.extra_bit 1 331 143</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">4</td><td style="text-align:center"> 20</td><td style="text-align:center"> 0 9 0</td><td style="text-align:center">.extra_bit 1 330 142</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">5</td><td style="text-align:center"> 94</td><td style="text-align:center">13 9 0</td><td style="text-align:center">.extra_bit 1 331 142</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">6</td><td style="text-align:center"> 49</td><td style="text-align:center"> 6 0 1</td><td style="text-align:center">.extra_bit 0 330 143</td></tr> +<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">7</td><td style="text-align:center">129</td><td style="text-align:center"> 6 17 1</td><td style="text-align:center">.extra_bit 0 331 143</td></tr> </table> -</p> <p> Signals internal to the FPGA can also be routed to the global nets. This is done by routing the signal -to the <tt>fabout</tt> net on an IO tile. The same set of I/O tiles is used for this, but in this +to the <span style="font-family:monospace">fabout</span> net on an IO tile. The same set of I/O tiles is used for this, but in this case each of the I/O tiles corresponds to a different global net: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>Glb Net</th> -<td align="center">0</td> -<td align="center">1</td> -<td align="center">2</td> -<td align="center">3</td> -<td align="center">4</td> -<td align="center">5</td> -<td align="center">6</td> -<td align="center">7</td></tr> +<td style="text-align:center">0</td> +<td style="text-align:center">1</td> +<td style="text-align:center">2</td> +<td style="text-align:center">3</td> +<td style="text-align:center">4</td> +<td style="text-align:center">5</td> +<td style="text-align:center">6</td> +<td style="text-align:center">7</td></tr> <tr><th>IO Tile</th> -<td style="white-space: pre; font-family: monospace" align="center"> 7 0</td> -<td style="white-space: pre; font-family: monospace" align="center"> 7 17</td> -<td style="white-space: pre; font-family: monospace" align="center">13 9</td> -<td style="white-space: pre; font-family: monospace" align="center"> 0 9</td> -<td style="white-space: pre; font-family: monospace" align="center"> 6 17</td> -<td style="white-space: pre; font-family: monospace" align="center"> 6 0</td> -<td style="white-space: pre; font-family: monospace" align="center"> 0 8</td> -<td style="white-space: pre; font-family: monospace" align="center">13 8</td></tr> +<td style="white-space: pre; font-family: monospace; text-align:center"> 7 0</td> +<td style="white-space: pre; font-family: monospace; text-align:center"> 7 17</td> +<td style="white-space: pre; font-family: monospace; text-align:center">13 9</td> +<td style="white-space: pre; font-family: monospace; text-align:center"> 0 9</td> +<td style="white-space: pre; font-family: monospace; text-align:center"> 6 17</td> +<td style="white-space: pre; font-family: monospace; text-align:center"> 6 0</td> +<td style="white-space: pre; font-family: monospace; text-align:center"> 0 8</td> +<td style="white-space: pre; font-family: monospace; text-align:center">13 8</td></tr> </table> -</p> -<p><a href="colbuf.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="colbuf.svg" border="0"></a></p> +<p><a href="colbuf.svg"><img alt="Column Buffers" style="float:right; padding:1em; padding-top:0; border:0" height="200" src="colbuf.svg"></a></p> <h3>Column Buffer Control Bits</h3> @@ -344,147 +357,142 @@ IO columns. <h2>Warmboot</h2> <p> -The <tt>SB_WARMBOOT</tt> primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell -are driven by the <tt>fabout</tt> signal from three IO tiles. In HX1K chips the tiles connected to the -<tt>SB_WARMBOOT</tt> primitive are: +The <span style="font-family:monospace">SB_WARMBOOT</span> primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell +are driven by the <span style="font-family:monospace">fabout</span> signal from three IO tiles. In HX1K chips the tiles connected to the +<span style="font-family:monospace">SB_WARMBOOT</span> primitive are: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>Warmboot Pin</th><th>IO Tile</th></tr> -<tr><td>BOOT</td><td><tt>12 0</tt></td></tr> -<tr><td>S0</td><td><tt>13 1</tt></td></tr> -<tr><td>S1</td><td><tt>13 2</tt></td></tr> +<tr><td>BOOT</td><td><span style="font-family:monospace">12 0</span></td></tr> +<tr><td>S0</td><td><span style="font-family:monospace">13 1</span></td></tr> +<tr><td>S1</td><td><span style="font-family:monospace">13 2</span></td></tr> </table> -</p> <h2>PLL Cores</h2> <p> -The PLL primitives in iCE40 FPGAs are configured using the <tt>PLLCONFIG_*</tt> +The PLL primitives in iCE40 FPGAs are configured using the <span style="font-family:monospace">PLLCONFIG_*</span> bits in the IO tiles. The configuration for a single PLL cell is spread out over many IO tiles. For example, the PLL cell in the 1K chip are configured as follows (bits listed from LSB to MSB): </p> -<p align="center"> -<table cellpadding="10"><tr><td valign="top"> +<table class="xtab"> +<tr><td> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>IO Tile</th><th>Config Bit</th><th>SB_PLL40_* Parameter</th></tr> -<tr><td>0 3</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="3">Select PLL Type:<br/> +<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_5</span></td><td rowspan="3">Select PLL Type:<br/> 000 = DISABLED<br/> 010 = SB_PLL40_PAD<br/> 100 = SB_PLL40_2_PAD<br/> 110 = SB_PLL40_2F_PAD<br/> 011 = SB_PLL40_CORE<br/> 111 = SB_PLL40_2F_CORE</td></tr> -<tr><td>0 5</td><td><tt>PLLCONFIG_1</tt></td></tr> -<tr><td>0 5</td><td><tt>PLLCONFIG_3</tt></td></tr> +<tr><td>0 5</td><td><span style="font-family:monospace">PLLCONFIG_1</span></td></tr> +<tr><td>0 5</td><td><span style="font-family:monospace">PLLCONFIG_3</span></td></tr> -<tr><td>0 5</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="3"><tt>FEEDBACK_PATH</tt><br/> +<tr><td>0 5</td><td><span style="font-family:monospace">PLLCONFIG_5</span></td><td rowspan="3"><span style="font-family:monospace">FEEDBACK_PATH</span><br/> 000 = "DELAY"<br/> 001 = "SIMPLE"<br/> 010 = "PHASE_AND_DELAY"<br/> 110 = "EXTERNAL"</td></tr> -<tr><td>0 2</td><td><tt>PLLCONFIG_9</tt></td></tr> -<tr><td>0 3</td><td><tt>PLLCONFIG_1</tt></td></tr> +<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_9</span></td></tr> +<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_1</span></td></tr> -<tr><td>0 4</td><td><tt>PLLCONFIG_4</tt></td><td rowspan="1"><tt>DELAY_ADJUSTMENT_MODE_FEEDBACK</tt><br/> +<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_4</span></td><td rowspan="1"><span style="font-family:monospace">DELAY_ADJUSTMENT_MODE_FEEDBACK</span><br/> 0 = "FIXED"<br/> 1 = "DYNAMIC"</td></tr> -<tr><td>0 4</td><td><tt>PLLCONFIG_9</tt></td><td rowspan="1"><tt>DELAY_ADJUSTMENT_MODE_RELATIVE</tt><br/> +<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_9</span></td><td rowspan="1"><span style="font-family:monospace">DELAY_ADJUSTMENT_MODE_RELATIVE</span><br/> 0 = "FIXED"<br/> 1 = "DYNAMIC"</td></tr> -<tr><td>0 3</td><td><tt>PLLCONFIG_6</tt></td><td rowspan="2"><tt>PLLOUT_SELECT<br/>PLLOUT_SELECT_PORTA</tt><br/> +<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_6</span></td><td rowspan="2"><span style="font-family:monospace">PLLOUT_SELECT<br/>PLLOUT_SELECT_PORTA</span><br/> 00 = "GENCLK"<br/> 01 = "GENCLK_HALF"<br/> 10 = "SHIFTREG_90deg"<br/> 11 = "SHIFTREG_0deg"</td></tr> -<tr><td>0 3</td><td><tt>PLLCONFIG_7</tt></td></tr> +<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_7</span></td></tr> -<tr><td>0 3</td><td><tt>PLLCONFIG_2</tt></td><td rowspan="2"><tt>PLLOUT_SELECT_PORTB</tt><br/> +<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_2</span></td><td rowspan="2"><span style="font-family:monospace">PLLOUT_SELECT_PORTB</span><br/> 00 = "GENCLK"<br/> 01 = "GENCLK_HALF"<br/> 10 = "SHIFTREG_90deg"<br/> 11 = "SHIFTREG_0deg"</td></tr> -<tr><td>0 3</td><td><tt>PLLCONFIG_3</tt></td></tr> +<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_3</span></td></tr> -<tr><td>0 3</td><td><tt>PLLCONFIG_4</tt></td><td rowspan="1"><tt>SHIFTREG_DIV_MODE</tt></td></tr> +<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_4</span></td><td rowspan="1"><span style="font-family:monospace">SHIFTREG_DIV_MODE</span></td></tr> -<tr><td>0 3</td><td><tt>PLLCONFIG_8</tt></td><td rowspan="1"><tt>TEST_MODE</tt></td></tr> +<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_8</span></td><td rowspan="1"><span style="font-family:monospace">TEST_MODE</span></td></tr> -</table></td><td valign="top"> +</table></td><td> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>IO Tile</th><th>Config Bit</th><th>SB_PLL40_* Parameter</th></tr> -<tr><td>0 3</td><td><tt>PLLCONFIG_9</tt></td><td rowspan="4"><tt>FDA_FEEDBACK</tt></td></tr> -<tr><td>0 4</td><td><tt>PLLCONFIG_1</tt></td></tr> -<tr><td>0 4</td><td><tt>PLLCONFIG_2</tt></td></tr> -<tr><td>0 4</td><td><tt>PLLCONFIG_3</tt></td></tr> - -<tr><td>0 5</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="4"><tt>FDA_RELATIVE</tt></td></tr> -<tr><td>0 4</td><td><tt>PLLCONFIG_6</tt></td></tr> -<tr><td>0 4</td><td><tt>PLLCONFIG_7</tt></td></tr> -<tr><td>0 4</td><td><tt>PLLCONFIG_8</tt></td></tr> - -<tr><td>0 1</td><td><tt>PLLCONFIG_1</tt></td><td rowspan="4"><tt>DIVR</tt></td></tr> -<tr><td>0 1</td><td><tt>PLLCONFIG_2</tt></td></tr> -<tr><td>0 1</td><td><tt>PLLCONFIG_3</tt></td></tr> -<tr><td>0 1</td><td><tt>PLLCONFIG_4</tt></td></tr> - -<tr><td>0 1</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="7"><tt>DIVF</tt></td></tr> -<tr><td>0 1</td><td><tt>PLLCONFIG_6</tt></td></tr> -<tr><td>0 1</td><td><tt>PLLCONFIG_7</tt></td></tr> -<tr><td>0 1</td><td><tt>PLLCONFIG_8</tt></td></tr> -<tr><td>0 1</td><td><tt>PLLCONFIG_9</tt></td></tr> -<tr><td>0 2</td><td><tt>PLLCONFIG_1</tt></td></tr> -<tr><td>0 2</td><td><tt>PLLCONFIG_2</tt></td></tr> - -<tr><td>0 2</td><td><tt>PLLCONFIG_3</tt></td><td rowspan="3"><tt>DIVQ</tt></td></tr> -<tr><td>0 2</td><td><tt>PLLCONFIG_4</tt></td></tr> -<tr><td>0 2</td><td><tt>PLLCONFIG_5</tt></td></tr> - -<tr><td>0 2</td><td><tt>PLLCONFIG_6</tt></td><td rowspan="3"><tt>FILTER_RANGE</tt></td></tr> -<tr><td>0 2</td><td><tt>PLLCONFIG_7</tt></td></tr> -<tr><td>0 2</td><td><tt>PLLCONFIG_8</tt></td></tr> +<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_9</span></td><td rowspan="4"><span style="font-family:monospace">FDA_FEEDBACK</span></td></tr> +<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_1</span></td></tr> +<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_2</span></td></tr> +<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_3</span></td></tr> + +<tr><td>0 5</td><td><span style="font-family:monospace">PLLCONFIG_5</span></td><td rowspan="4"><span style="font-family:monospace">FDA_RELATIVE</span></td></tr> +<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_6</span></td></tr> +<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_7</span></td></tr> +<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_8</span></td></tr> + +<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_1</span></td><td rowspan="4"><span style="font-family:monospace">DIVR</span></td></tr> +<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_2</span></td></tr> +<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_3</span></td></tr> +<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_4</span></td></tr> + +<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_5</span></td><td rowspan="7"><span style="font-family:monospace">DIVF</span></td></tr> +<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_6</span></td></tr> +<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_7</span></td></tr> +<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_8</span></td></tr> +<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_9</span></td></tr> +<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_1</span></td></tr> +<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_2</span></td></tr> + +<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_3</span></td><td rowspan="3"><span style="font-family:monospace">DIVQ</span></td></tr> +<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_4</span></td></tr> +<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_5</span></td></tr> + +<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_6</span></td><td rowspan="3"><span style="font-family:monospace">FILTER_RANGE</span></td></tr> +<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_7</span></td></tr> +<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_8</span></td></tr> </table> </table> -</p> <p> -The PLL inputs are routed to the PLL via the <tt>fabout</tt> signal from various IO tiles. The non-clock -PLL outputs are routed via otherwise unused <tt>neigh_op_*</tt> signals in fabric corners. For example in case +The PLL inputs are routed to the PLL via the <span style="font-family:monospace">fabout</span> signal from various IO tiles. The non-clock +PLL outputs are routed via otherwise unused <span style="font-family:monospace">neigh_op_*</span> signals in fabric corners. For example in case of the 1k chip: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>Tile</th><th>Net-Segment</th><th>SB_PLL40_* Port Name</th></tr> -<tr><td>0 1</td><td><tt>fabout</tt></td><td rowspan="1"><tt>REFERENCECLK</tt></td></tr> -<tr><td>0 2</td><td><tt>fabout</tt></td><td rowspan="1"><tt>EXTFEEDBACK</tt></td></tr> -<tr><td>0 4</td><td><tt>fabout</tt></td><td rowspan="8"><tt>DYNAMICDELAY</tt></td></tr> -<tr><td>0 5</td><td><tt>fabout</tt></td></tr> -<tr><td>0 6</td><td><tt>fabout</tt></td></tr> -<tr><td>0 10</td><td><tt>fabout</tt></td></tr> -<tr><td>0 11</td><td><tt>fabout</tt></td></tr> -<tr><td>0 12</td><td><tt>fabout</tt></td></tr> -<tr><td>0 13</td><td><tt>fabout</tt></td></tr> -<tr><td>0 14</td><td><tt>fabout</tt></td></tr> -<tr><td>1 1</td><td><tt>neigh_op_bnl_1</tt></td><td rowspan="1"><tt>LOCK</tt></td></tr> -<tr><td>1 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>BYPASS</tt></td></tr> -<tr><td>2 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>RESETB</tt></td></tr> -<tr><td>5 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>LATCHINPUTVALUE</tt></td></tr> -<tr><td>12 1</td><td><tt>neigh_op_bnl_1</tt></td><td rowspan="1"><tt>SDO</tt></td></tr> -<tr><td>4 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>SDI</tt></td></tr> -<tr><td>5 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>SCLK</tt></td></tr> +<tr><td>0 1</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">REFERENCECLK</span></td></tr> +<tr><td>0 2</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">EXTFEEDBACK</span></td></tr> +<tr><td>0 4</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="8"><span style="font-family:monospace">DYNAMICDELAY</span></td></tr> +<tr><td>0 5</td><td><span style="font-family:monospace">fabout</span></td></tr> +<tr><td>0 6</td><td><span style="font-family:monospace">fabout</span></td></tr> +<tr><td>0 10</td><td><span style="font-family:monospace">fabout</span></td></tr> +<tr><td>0 11</td><td><span style="font-family:monospace">fabout</span></td></tr> +<tr><td>0 12</td><td><span style="font-family:monospace">fabout</span></td></tr> +<tr><td>0 13</td><td><span style="font-family:monospace">fabout</span></td></tr> +<tr><td>0 14</td><td><span style="font-family:monospace">fabout</span></td></tr> +<tr><td>1 1</td><td><span style="font-family:monospace">neigh_op_bnl_1</span></td><td rowspan="1"><span style="font-family:monospace">LOCK</span></td></tr> +<tr><td>1 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">BYPASS</span></td></tr> +<tr><td>2 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">RESETB</span></td></tr> +<tr><td>5 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">LATCHINPUTVALUE</span></td></tr> +<tr><td>12 1</td><td><span style="font-family:monospace">neigh_op_bnl_1</span></td><td rowspan="1"><span style="font-family:monospace">SDO</span></td></tr> +<tr><td>4 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">SDI</span></td></tr> +<tr><td>5 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">SCLK</span></td></tr> </table> -</p> <p> The PLL clock outputs are fed directly into the input path of certain IO tiles. @@ -494,3 +502,4 @@ PIOs can only be used as output Pins by the FPGA fabric when the PLL ports are being used. </p> +</body></html> diff --git a/docs/logic_tile.html b/docs/logic_tile.html index 6404a80..67524bb 100644 --- a/docs/logic_tile.html +++ b/docs/logic_tile.html @@ -1,4 +1,18 @@ +<!DOCTYPE html> +<html><head><meta charset="UTF-8"> +<style> +.ctab { + margin-left: auto; + margin-right: auto; + border: 1px solid gray; +} +.ctab td, .ctab th { + padding: 3px; + border: 1px solid gray; +} +</style> <title>Project IceStorm – LOGIC Tile Documentation</title> +</head><body> <h1>Project IceStorm – LOGIC Tile Documentation</h1> <p> @@ -15,9 +29,9 @@ The <i>span-4</i> and <i>span-12</i> wires are the main interconnect resource in </p> <p> -The bits marked <tt>routing</tt> in the bitstream do enable switches (transfer gates) that can +The bits marked <span style="font-family:monospace">routing</span> in the bitstream do enable switches (transfer gates) that can be used to connect wire segments bidirectionally to each other in order to create larger -segments. The bits marked <tt>buffer</tt> in the bitstream enable tristate buffers that drive +segments. The bits marked <span style="font-family:monospace">buffer</span> in the bitstream enable tristate buffers that drive the signal in one direction from one wire to another. Both types of bits exist for routing between span-wires. See the auto generated documentation for the LOGIC Tile configuration bits for details. </p> @@ -28,21 +42,21 @@ Only directional tristate buffers are used to route signals between the span-wir <h3 style="clear:both">Span-4 Horizontal</h3> -<p><a href="sp4h.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="sp4h.svg" border="0"></a></p> +<p><a href="sp4h.svg"><img alt="Span-4 Horizontal" style="float:right; padding:1em; padding-top:0; border:0" height="200" src="sp4h.svg"></a></p> <p> The image on the right shows the <i>horizontal span-4</i> wires of a logic or ram cell (click to enlarge). </p> <p> -On the left side of the cell there are 48 connections named <tt>sp4_h_l_0</tt> to <tt>sp4_h_l_47</tt>. The lower 36 of those -wires are connected to <tt>sp4_h_r_12</tt> to <tt>sp4_h_r_47</tt> on the right side of the cell. (IceStorm normalizes this -wire names to <tt>sp4_h_r_0</tt> to <tt>sp4_h_r_35</tt>. Note: the Lattice tools use a different normalization scheme +On the left side of the cell there are 48 connections named <span style="font-family:monospace">sp4_h_l_0</span> to <span style="font-family:monospace">sp4_h_l_47</span>. The lower 36 of those +wires are connected to <span style="font-family:monospace">sp4_h_r_12</span> to <span style="font-family:monospace">sp4_h_r_47</span> on the right side of the cell. (IceStorm normalizes this +wire names to <span style="font-family:monospace">sp4_h_r_0</span> to <span style="font-family:monospace">sp4_h_r_35</span>. Note: the Lattice tools use a different normalization scheme for this wire names.) The wires connecting the left and right horizontal span-4 ports are pairwise crossed-out. </p> <p> -The wires <tt>sp4_h_l_36</tt> to <tt>sp4_h_l_47</tt> terminate in the cell, so do the wires <tt>sp4_h_r_0</tt> to <tt>sp4_h_r_11</tt>. +The wires <span style="font-family:monospace">sp4_h_l_36</span> to <span style="font-family:monospace">sp4_h_l_47</span> terminate in the cell, so do the wires <span style="font-family:monospace">sp4_h_r_0</span> to <span style="font-family:monospace">sp4_h_r_11</span>. </p> <p> @@ -51,55 +65,51 @@ both ends of the wire. </p> <p> -For example, the wire <tt>sp4_h_r_0</tt> in cell (x, y) has the following names: +For example, the wire <span style="font-family:monospace">sp4_h_r_0</span> in cell (x, y) has the following names: </p> -<p align="center"> -<table border> +<table class="ctab"> <tr><th>Cell Coordinates</th><th>sp4_h_l_* wire name</th><th>sp4_h_r_* wire name</th></tr> -<tr><td>x, y</td><td><tt>-</tt></td><td><tt>sp4_h_r_0</tt></td></tr> -<tr><td>x+1, y</td><td><tt>sp4_h_l_0</tt></td><td><tt>sp4_h_r_13</tt></td></tr> -<tr><td>x+2, y</td><td><tt>sp4_h_l_13</tt></td><td><tt>sp4_h_r_24</tt></td></tr> -<tr><td>x+3, y</td><td><tt>sp4_h_l_24</tt></td><td><tt>sp4_h_r_37</tt></td></tr> -<tr><td>x+4, y</td><td><tt>sp4_h_l_37</tt></td><td><tt>-</tt></td></tr> +<tr><td>x, y</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_h_r_0</span></td></tr> +<tr><td>x+1, y</td><td><span style="font-family:monospace">sp4_h_l_0</span></td><td><span style="font-family:monospace">sp4_h_r_13</span></td></tr> +<tr><td>x+2, y</td><td><span style="font-family:monospace">sp4_h_l_13</span></td><td><span style="font-family:monospace">sp4_h_r_24</span></td></tr> +<tr><td>x+3, y</td><td><span style="font-family:monospace">sp4_h_l_24</span></td><td><span style="font-family:monospace">sp4_h_r_37</span></td></tr> +<tr><td>x+4, y</td><td><span style="font-family:monospace">sp4_h_l_37</span></td><td><span style="font-family:monospace">-</span></td></tr> </table> -</p> <h3 style="clear:both">Span-4 Vertical</h3> -<p><a href="sp4v.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="sp4v.svg" border="0"></a></p> +<p><a href="sp4v.svg"><img alt="Span-4 Vertical" style="float:right; padding:1em; padding-top:0; border:0" height="200" src="sp4v.svg"></a></p> <p> The image on the right shows the <i>vertical span-4</i> wires of a logic or ram cell (click to enlarge). </p> <p> -Similar to the horizontal span-4 wires there are 48 connections on the top (<tt>sp4_v_t_0</tt> to <tt>sp4_v_t_47</tt>) and -48 connections on the bottom (<tt>sp4_v_b_0</tt> to <tt>sp4_v_b_47</tt>). The wires <tt>sp4_v_t_0</tt> to <tt>sp4_v_t_35</tt> -are connected to <tt>sp4_v_b_12</tt> to <tt>sp4_v_b_47</tt> (with pairwise crossing out). Wire names are normalized -to <tt>sp4_v_b_12</tt> to <tt>sp4_v_b_47</tt>. +Similar to the horizontal span-4 wires there are 48 connections on the top (<span style="font-family:monospace">sp4_v_t_0</span> to <span style="font-family:monospace">sp4_v_t_47</span>) and +48 connections on the bottom (<span style="font-family:monospace">sp4_v_b_0</span> to <span style="font-family:monospace">sp4_v_b_47</span>). The wires <span style="font-family:monospace">sp4_v_t_0</span> to <span style="font-family:monospace">sp4_v_t_35</span> +are connected to <span style="font-family:monospace">sp4_v_b_12</span> to <span style="font-family:monospace">sp4_v_b_47</span> (with pairwise crossing out). Wire names are normalized +to <span style="font-family:monospace">sp4_v_b_12</span> to <span style="font-family:monospace">sp4_v_b_47</span>. </p> <p> -But in addition to that, each cell also has access to <tt>sp4_v_b_0</tt> to <tt>sp4_v_b_47</tt> of its right neighbour. -This are the wires <tt>sp4_r_v_b_0</tt> to <tt>sp4_r_v_b_47</tt>. So over all a single vertical span-4 wire -connects 9 cells. For example, the wire <tt>sp4_v_b_0</tt> in cell (x, y) has the following names: +But in addition to that, each cell also has access to <span style="font-family:monospace">sp4_v_b_0</span> to <span style="font-family:monospace">sp4_v_b_47</span> of its right neighbour. +This are the wires <span style="font-family:monospace">sp4_r_v_b_0</span> to <span style="font-family:monospace">sp4_r_v_b_47</span>. So over all a single vertical span-4 wire +connects 9 cells. For example, the wire <span style="font-family:monospace">sp4_v_b_0</span> in cell (x, y) has the following names: </p> -<p align="center"> -<table border> +<table class="ctab"> <tr><th>Cell Coordinates</th><th>sp4_v_t_* wire name</th><th>sp4_v_b_* wire name</th><th>sp4_r_v_b_* wire name</th></tr> -<tr><td>x, y</td><td><tt>-</tt></td><td><tt>sp4_v_b_0</tt></td><td><tt>-</tt></td></tr> -<tr><td>x, y-1</td><td><tt>sp4_v_t_0</tt></td><td><tt>sp4_v_b_13</tt></td><td><tt>-</tt></td></tr> -<tr><td>x, y-2</td><td><tt>sp4_v_t_13</tt></td><td><tt>sp4_v_b_24</tt></td><td><tt>-</tt></td></tr> -<tr><td>x, y-3</td><td><tt>sp4_v_t_24</tt></td><td><tt>sp4_v_b_37</tt></td><td><tt>-</tt></td></tr> -<tr><td>x, y-4</td><td><tt>sp4_v_t_37</tt></td><td><tt>-</tt></td><td><tt>-</tt></td></tr> -<tr><td>x-1, y</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_0</tt></td></tr> -<tr><td>x-1, y-1</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_13</tt></td></tr> -<tr><td>x-1, y-2</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_24</tt></td></tr> -<tr><td>x-1, y-3</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_37</tt></td></tr> +<tr><td>x, y</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_v_b_0</span></td><td><span style="font-family:monospace">-</span></td></tr> +<tr><td>x, y-1</td><td><span style="font-family:monospace">sp4_v_t_0</span></td><td><span style="font-family:monospace">sp4_v_b_13</span></td><td><span style="font-family:monospace">-</span></td></tr> +<tr><td>x, y-2</td><td><span style="font-family:monospace">sp4_v_t_13</span></td><td><span style="font-family:monospace">sp4_v_b_24</span></td><td><span style="font-family:monospace">-</span></td></tr> +<tr><td>x, y-3</td><td><span style="font-family:monospace">sp4_v_t_24</span></td><td><span style="font-family:monospace">sp4_v_b_37</span></td><td><span style="font-family:monospace">-</span></td></tr> +<tr><td>x, y-4</td><td><span style="font-family:monospace">sp4_v_t_37</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">-</span></td></tr> +<tr><td>x-1, y</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_r_v_b_0</span></td></tr> +<tr><td>x-1, y-1</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_r_v_b_13</span></td></tr> +<tr><td>x-1, y-2</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_r_v_b_24</span></td></tr> +<tr><td>x-1, y-3</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_r_v_b_37</span></td></tr> </table> -</p> <h3 style="clear:both">Span-12 Horizontal and Vertical</h3> @@ -108,21 +118,21 @@ Similar to the span-4 wires there are also longer horizontal and vertical span-1 </p> <p> -There are 24 connections <tt>sp12_v_t_0</tt> to <tt>sp12_v_t_23</tt> on the top of the -cell and 24 connections <tt>sp12_v_b_0</tt> to <tt>sp12_v_b_23</tt> on the bottom of the -cell. The wires <tt>sp12_v_t_0</tt> to <tt>sp12_v_t_21</tt> are connected to -<tt>sp12_v_b_2</tt> to <tt>sp12_v_b_23</tt> (with pairwise crossing out). The connections -<tt>sp12_v_b_0</tt>, <tt>sp12_v_b_1</tt>, <tt>sp12_v_t_22</tt>, and <tt>sp12_v_t_23</tt> -terminate in the cell. Wire names are normalized to <tt>sp12_v_b_2</tt> to <tt>sp12_v_b_23</tt>. +There are 24 connections <span style="font-family:monospace">sp12_v_t_0</span> to <span style="font-family:monospace">sp12_v_t_23</span> on the top of the +cell and 24 connections <span style="font-family:monospace">sp12_v_b_0</span> to <span style="font-family:monospace">sp12_v_b_23</span> on the bottom of the +cell. The wires <span style="font-family:monospace">sp12_v_t_0</span> to <span style="font-family:monospace">sp12_v_t_21</span> are connected to +<span style="font-family:monospace">sp12_v_b_2</span> to <span style="font-family:monospace">sp12_v_b_23</span> (with pairwise crossing out). The connections +<span style="font-family:monospace">sp12_v_b_0</span>, <span style="font-family:monospace">sp12_v_b_1</span>, <span style="font-family:monospace">sp12_v_t_22</span>, and <span style="font-family:monospace">sp12_v_t_23</span> +terminate in the cell. Wire names are normalized to <span style="font-family:monospace">sp12_v_b_2</span> to <span style="font-family:monospace">sp12_v_b_23</span>. </p> <p> -There are also 24 connections <tt>sp12_h_l_0</tt> to <tt>sp12_h_l_23</tt> on the left of the -cell and 24 connections <tt>sp12_h_r_0</tt> to <tt>sp12_h_r_23</tt> on the right of the -cell. The wires <tt>sp12_h_l_0</tt> to <tt>sp12_h_l_21</tt> are connected to -<tt>sp12_h_r_2</tt> to <tt>sp12_h_r_23</tt> (with pairwise crossing out). The connections -<tt>sp12_h_r_0</tt>, <tt>sp12_h_r_1</tt>, <tt>sp12_h_l_22</tt>, and <tt>sp12_h_l_23</tt> -terminate in the cell. Wire names are normalized to <tt>sp12_v_r_2</tt> to <tt>sp12_h_r_23</tt>. +There are also 24 connections <span style="font-family:monospace">sp12_h_l_0</span> to <span style="font-family:monospace">sp12_h_l_23</span> on the left of the +cell and 24 connections <span style="font-family:monospace">sp12_h_r_0</span> to <span style="font-family:monospace">sp12_h_r_23</span> on the right of the +cell. The wires <span style="font-family:monospace">sp12_h_l_0</span> to <span style="font-family:monospace">sp12_h_l_21</span> are connected to +<span style="font-family:monospace">sp12_h_r_2</span> to <span style="font-family:monospace">sp12_h_r_23</span> (with pairwise crossing out). The connections +<span style="font-family:monospace">sp12_h_r_0</span>, <span style="font-family:monospace">sp12_h_r_1</span>, <span style="font-family:monospace">sp12_h_l_22</span>, and <span style="font-family:monospace">sp12_h_l_23</span> +terminate in the cell. Wire names are normalized to <span style="font-family:monospace">sp12_v_r_2</span> to <span style="font-family:monospace">sp12_h_r_23</span>. </p> <h2>Local Tracks</h2> @@ -135,7 +145,7 @@ signals from the local tracks can be routed to the logic cell inputs. <p> Each logic tile has 32 local tracks. They are organized in 4 groups of 8 wires each: -<tt>local_g0_0</tt> to <tt>local_g3_7</tt>. +<span style="font-family:monospace">local_g0_0</span> to <span style="font-family:monospace">local_g3_7</span>. </p> <p> @@ -146,71 +156,59 @@ mix of 16 signals for each local track. <p> The buffer driving the local track has 5 configuration bits. One enable bit and 4 bits that select -the input wire. For example for <tt>local_g0_0</tt> (copy&paste from the bitstream doku): +the input wire. For example for <span style="font-family:monospace">local_g0_0</span> (copy&paste from the bitstream doku): </p> -<p align="center"> -<table border=""><tbody><tr> -<th style="width:5em"><a name="B.0.14">B0[14]</a></th> -<th style="width:5em"><a name="B.1.14">B1[14]</a></th> -<th style="width:5em"><a name="B.1.15">B1[15]</a></th> -<th style="width:5em"><a name="B.1.16">B1[16]</a></th> -<th style="width:5em"><a name="B.1.17">B1[17]</a></th> +<table class="ctab"> +<tr><th style="width:5em">B0[14]</th><th style="width:5em">B1[14]</th><th style="width:5em">B1[15]</th><th style="width:5em">B1[16]</th> <th style="width:5em">B1[17]</th> <th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_r_v_b_24</tt></td><td><tt>local_g0_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_8</tt></td><td><tt>local_g0_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_bot_0</tt></td><td><tt>local_g0_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_16</tt></td><td><tt>local_g0_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_r_v_b_35</tt></td><td><tt>local_g0_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td 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align="center">buffer</td><td><tt>sp4_v_b_0</tt></td><td><tt>local_g0_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_lft_0</tt></td><td><tt>local_g0_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_8</tt></td><td><tt>local_g0_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_bnr_0</tt></td><td><tt>local_g0_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_8</tt></td><td><tt>local_g0_0</tt></td></tr> -<tr><td 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+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_h_r_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">lutff_0/out</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_v_b_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">neigh_op_lft_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_h_r_8</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">neigh_op_bnr_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_v_b_8</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp12_h_r_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_h_r_16</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr> +</table> <p> Then the signals on the local tracks can be routed to the input pins of the logic cells. Like before, not every local track can be routed to every logic cell input pin. Instead there is a different mix -of 16 local track for each logic cell input. For example for <tt>lutff_0/in_0</tt>: +of 16 local track for each logic cell input. For example for <span style="font-family:monospace">lutff_0/in_0</span>: </p> -<p align="center"> -<table border=""><tbody><tr> -<th style="width:5em"><a name="B.0.26">B0[26]</a></th> -<th style="width:5em"><a name="B.1.26">B1[26]</a></th> -<th style="width:5em"><a name="B.1.27">B1[27]</a></th> -<th style="width:5em"><a name="B.1.28">B1[28]</a></th> -<th style="width:5em"><a name="B.1.29">B1[29]</a></th> +<table class="ctab"> +<tr><th style="width:5em">B0[26]</th><th style="width:5em">B1[26]</th><th style="width:5em">B1[27]</th><th style="width:5em">B1[28]</th><th style="width:5em">B1[29]</th> <th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_0</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_0</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_1</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_1</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_2</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_2</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_3</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_3</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_4</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_4</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_5</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_5</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_6</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_6</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_7</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_7</tt></td><td><tt>lutff_0/in_0</tt></td></tr> -</tbody></table> -</p> - -<p> -The 8 global nets on the iCE40 can be routed to the local track via the <tt>glb2local_0</tt> to <tt>glb2local_3</tt> +<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g0_0</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g2_0</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g1_1</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g3_1</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g0_2</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g2_2</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g1_3</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g3_3</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g0_4</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g2_4</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g1_5</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g3_5</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g0_6</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g2_6</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g1_7</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g3_7</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr> +</table> + +<p> +The 8 global nets on the iCE40 can be routed to the local track via the <span style="font-family:monospace">glb2local_0</span> to <span style="font-family:monospace">glb2local_3</span> nets using a similar two-stage process. The logic block clock-enable and set-reset inputs can be driven directly from one of 4 global nets or from one of 4 local tracks. The logic block clock input can be driven from any of the global nets and from a few local tracks. See the bitstream documentation for details. @@ -227,97 +225,93 @@ or asynchronous exist for each logic cell individually. </p> <p> -Each LUT <i>i</i> has four input wires <tt>lutff_<i>i</i>/in_0</tt> to <tt>lutff_<i>i</i>/in_3</tt>. Input -<tt>lutff_<i>i</i>/in_3</tt> can be configured to be driven by the carry output of the previous logic cell, -or by <tt>carry_in_mux</tt> in case of <i>i</i>=0. Input <tt>lutff_<i>i</i>/in_2</tt> can be configured to +Each LUT <i>i</i> has four input wires <span style="font-family:monospace">lutff_<i>i</i>/in_0</span> to <span style="font-family:monospace">lutff_<i>i</i>/in_3</span>. Input +<span style="font-family:monospace">lutff_<i>i</i>/in_3</span> can be configured to be driven by the carry output of the previous logic cell, +or by <span style="font-family:monospace">carry_in_mux</span> in case of <i>i</i>=0. Input <span style="font-family:monospace">lutff_<i>i</i>/in_2</span> can be configured to be driven by the output of the previous LUT for <i>i</i>>0. The LUT uses its 4 input signals to -calculate <tt>lutff_<i>i</i>/out</tt>. +calculate <span style="font-family:monospace">lutff_<i>i</i>/out</span>. </p> <p> -The carry unit calculates <tt>lutff_<i>i</i>/cout</tt> = <tt>lutff_<i>i</i>/in_1</tt> + <tt>lutff_<i>i</i>/in_2</tt> + <tt>lutff_<i>(i-1)</i>/cout</tt> > 1</tt>. In case of <i>i</i>=0, <tt>carry_in_mux</tt> is used as third input. <tt>carry_in_mux</tt> can be configured to be constant 0, 1 or the <tt>lutff_7/cout</tt> signal from the logic tile below. +The carry unit calculates <span style="font-family:monospace">lutff_<i>i</i>/cout</span> = <span style="font-family:monospace">lutff_<i>i</i>/in_1</span> + <span style="font-family:monospace">lutff_<i>i</i>/in_2</span> + <span style="font-family:monospace">lutff_<i>(i-1)</i>/cout</span> > 1. In case of <i>i</i>=0, <span style="font-family:monospace">carry_in_mux</span> is used as third input. <span style="font-family:monospace">carry_in_mux</span> can be configured to be constant 0, 1 or the <span style="font-family:monospace">lutff_7/cout</span> signal from the logic tile below. </p> <p> Part of the functionality described above is documented as part of the routing -bitstream documentation (see the buffers for <tt>lutff_</tt> inputs). The <tt>NegClk</tt> -bit switches all 8 FFs in the tile to negative edge mode. The <tt>CarryInSet</tt> -bit drives the <tt>carry_in_mux</tt> high (it defaults to low when not driven via the buffer from -<tt>carry_in</tt>). +bitstream documentation (see the buffers for <span style="font-family:monospace">lutff_</span> inputs). The <span style="font-family:monospace">NegClk</span> +bit switches all 8 FFs in the tile to negative edge mode. The <span style="font-family:monospace">CarryInSet</span> +bit drives the <span style="font-family:monospace">carry_in_mux</span> high (it defaults to low when not driven via the buffer from +<span style="font-family:monospace">carry_in</span>). </p> <p> -The remaining functions of the logic cell are configured via the <tt>LC_<i>i</i></tt> bits. This +The remaining functions of the logic cell are configured via the <span style="font-family:monospace">LC_<i>i</i></span> bits. This are 20 bit per logic cell. We have arbitrarily labeled those bits as follows: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>Label</th><th>LC_0</th><th>LC_1</th><th>LC_2</th><th>LC_3</th><th>LC_4</th><th>LC_5</th><th>LC_6</th><th>LC_7</th></tr> -<tr><td>LC_<i>i</i>[0]</tt></td><td>B0[36]</td><td>B2[36]</td><td>B4[36]</td><td>B6[36]</td><td>B8[36]</td><td>B10[36]</td><td>B12[36]</td><td>B14[36]</td></tr> -<tr><td>LC_<i>i</i>[1]</tt></td><td>B0[37]</td><td>B2[37]</td><td>B4[37]</td><td>B6[37]</td><td>B8[37]</td><td>B10[37]</td><td>B12[37]</td><td>B14[37]</td></tr> -<tr><td>LC_<i>i</i>[2]</tt></td><td>B0[38]</td><td>B2[38]</td><td>B4[38]</td><td>B6[38]</td><td>B8[38]</td><td>B10[38]</td><td>B12[38]</td><td>B14[38]</td></tr> -<tr><td>LC_<i>i</i>[3]</tt></td><td>B0[39]</td><td>B2[39]</td><td>B4[39]</td><td>B6[39]</td><td>B8[39]</td><td>B10[39]</td><td>B12[39]</td><td>B14[39]</td></tr> -<tr><td>LC_<i>i</i>[4]</tt></td><td>B0[40]</td><td>B2[40]</td><td>B4[40]</td><td>B6[40]</td><td>B8[40]</td><td>B10[40]</td><td>B12[40]</td><td>B14[40]</td></tr> -<tr><td>LC_<i>i</i>[5]</tt></td><td>B0[41]</td><td>B2[41]</td><td>B4[41]</td><td>B6[41]</td><td>B8[41]</td><td>B10[41]</td><td>B12[41]</td><td>B14[41]</td></tr> -<tr><td>LC_<i>i</i>[6]</tt></td><td>B0[42]</td><td>B2[42]</td><td>B4[42]</td><td>B6[42]</td><td>B8[42]</td><td>B10[42]</td><td>B12[42]</td><td>B14[42]</td></tr> -<tr><td>LC_<i>i</i>[7]</tt></td><td>B0[43]</td><td>B2[43]</td><td>B4[43]</td><td>B6[43]</td><td>B8[43]</td><td>B10[43]</td><td>B12[43]</td><td>B14[43]</td></tr> -<tr><td>LC_<i>i</i>[8]</tt></td><td>B0[44]</td><td>B2[44]</td><td>B4[44]</td><td>B6[44]</td><td>B8[44]</td><td>B10[44]</td><td>B12[44]</td><td>B14[44]</td></tr> -<tr><td>LC_<i>i</i>[9]</tt></td><td>B0[45]</td><td>B2[45]</td><td>B4[45]</td><td>B6[45]</td><td>B8[45]</td><td>B10[45]</td><td>B12[45]</td><td>B14[45]</td></tr> -<tr><td>LC_<i>i</i>[10]</tt></td><td>B1[36]</td><td>B3[36]</td><td>B5[36]</td><td>B7[36]</td><td>B9[36]</td><td>B11[36]</td><td>B13[36]</td><td>B15[36]</td></tr> -<tr><td>LC_<i>i</i>[11]</tt></td><td>B1[37]</td><td>B3[37]</td><td>B5[37]</td><td>B7[37]</td><td>B9[37]</td><td>B11[37]</td><td>B13[37]</td><td>B15[37]</td></tr> -<tr><td>LC_<i>i</i>[12]</tt></td><td>B1[38]</td><td>B3[38]</td><td>B5[38]</td><td>B7[38]</td><td>B9[38]</td><td>B11[38]</td><td>B13[38]</td><td>B15[38]</td></tr> -<tr><td>LC_<i>i</i>[13]</tt></td><td>B1[39]</td><td>B3[39]</td><td>B5[39]</td><td>B7[39]</td><td>B9[39]</td><td>B11[39]</td><td>B13[39]</td><td>B15[39]</td></tr> -<tr><td>LC_<i>i</i>[14]</tt></td><td>B1[40]</td><td>B3[40]</td><td>B5[40]</td><td>B7[40]</td><td>B9[40]</td><td>B11[40]</td><td>B13[40]</td><td>B15[40]</td></tr> -<tr><td>LC_<i>i</i>[15]</tt></td><td>B1[41]</td><td>B3[41]</td><td>B5[41]</td><td>B7[41]</td><td>B9[41]</td><td>B11[41]</td><td>B13[41]</td><td>B15[41]</td></tr> -<tr><td>LC_<i>i</i>[16]</tt></td><td>B1[42]</td><td>B3[42]</td><td>B5[42]</td><td>B7[42]</td><td>B9[42]</td><td>B11[42]</td><td>B13[42]</td><td>B15[42]</td></tr> -<tr><td>LC_<i>i</i>[17]</tt></td><td>B1[43]</td><td>B3[43]</td><td>B5[43]</td><td>B7[43]</td><td>B9[43]</td><td>B11[43]</td><td>B13[43]</td><td>B15[43]</td></tr> -<tr><td>LC_<i>i</i>[18]</tt></td><td>B1[44]</td><td>B3[44]</td><td>B5[44]</td><td>B7[44]</td><td>B9[44]</td><td>B11[44]</td><td>B13[44]</td><td>B15[44]</td></tr> -<tr><td>LC_<i>i</i>[19]</tt></td><td>B1[45]</td><td>B3[45]</td><td>B5[45]</td><td>B7[45]</td><td>B9[45]</td><td>B11[45]</td><td>B13[45]</td><td>B15[45]</td></tr> +<tr><td>LC_<i>i</i>[0]</td><td>B0[36]</td><td>B2[36]</td><td>B4[36]</td><td>B6[36]</td><td>B8[36]</td><td>B10[36]</td><td>B12[36]</td><td>B14[36]</td></tr> +<tr><td>LC_<i>i</i>[1]</td><td>B0[37]</td><td>B2[37]</td><td>B4[37]</td><td>B6[37]</td><td>B8[37]</td><td>B10[37]</td><td>B12[37]</td><td>B14[37]</td></tr> +<tr><td>LC_<i>i</i>[2]</td><td>B0[38]</td><td>B2[38]</td><td>B4[38]</td><td>B6[38]</td><td>B8[38]</td><td>B10[38]</td><td>B12[38]</td><td>B14[38]</td></tr> +<tr><td>LC_<i>i</i>[3]</td><td>B0[39]</td><td>B2[39]</td><td>B4[39]</td><td>B6[39]</td><td>B8[39]</td><td>B10[39]</td><td>B12[39]</td><td>B14[39]</td></tr> +<tr><td>LC_<i>i</i>[4]</td><td>B0[40]</td><td>B2[40]</td><td>B4[40]</td><td>B6[40]</td><td>B8[40]</td><td>B10[40]</td><td>B12[40]</td><td>B14[40]</td></tr> +<tr><td>LC_<i>i</i>[5]</td><td>B0[41]</td><td>B2[41]</td><td>B4[41]</td><td>B6[41]</td><td>B8[41]</td><td>B10[41]</td><td>B12[41]</td><td>B14[41]</td></tr> +<tr><td>LC_<i>i</i>[6]</td><td>B0[42]</td><td>B2[42]</td><td>B4[42]</td><td>B6[42]</td><td>B8[42]</td><td>B10[42]</td><td>B12[42]</td><td>B14[42]</td></tr> +<tr><td>LC_<i>i</i>[7]</td><td>B0[43]</td><td>B2[43]</td><td>B4[43]</td><td>B6[43]</td><td>B8[43]</td><td>B10[43]</td><td>B12[43]</td><td>B14[43]</td></tr> +<tr><td>LC_<i>i</i>[8]</td><td>B0[44]</td><td>B2[44]</td><td>B4[44]</td><td>B6[44]</td><td>B8[44]</td><td>B10[44]</td><td>B12[44]</td><td>B14[44]</td></tr> +<tr><td>LC_<i>i</i>[9]</td><td>B0[45]</td><td>B2[45]</td><td>B4[45]</td><td>B6[45]</td><td>B8[45]</td><td>B10[45]</td><td>B12[45]</td><td>B14[45]</td></tr> +<tr><td>LC_<i>i</i>[10]</td><td>B1[36]</td><td>B3[36]</td><td>B5[36]</td><td>B7[36]</td><td>B9[36]</td><td>B11[36]</td><td>B13[36]</td><td>B15[36]</td></tr> +<tr><td>LC_<i>i</i>[11]</td><td>B1[37]</td><td>B3[37]</td><td>B5[37]</td><td>B7[37]</td><td>B9[37]</td><td>B11[37]</td><td>B13[37]</td><td>B15[37]</td></tr> +<tr><td>LC_<i>i</i>[12]</td><td>B1[38]</td><td>B3[38]</td><td>B5[38]</td><td>B7[38]</td><td>B9[38]</td><td>B11[38]</td><td>B13[38]</td><td>B15[38]</td></tr> +<tr><td>LC_<i>i</i>[13]</td><td>B1[39]</td><td>B3[39]</td><td>B5[39]</td><td>B7[39]</td><td>B9[39]</td><td>B11[39]</td><td>B13[39]</td><td>B15[39]</td></tr> +<tr><td>LC_<i>i</i>[14]</td><td>B1[40]</td><td>B3[40]</td><td>B5[40]</td><td>B7[40]</td><td>B9[40]</td><td>B11[40]</td><td>B13[40]</td><td>B15[40]</td></tr> +<tr><td>LC_<i>i</i>[15]</td><td>B1[41]</td><td>B3[41]</td><td>B5[41]</td><td>B7[41]</td><td>B9[41]</td><td>B11[41]</td><td>B13[41]</td><td>B15[41]</td></tr> +<tr><td>LC_<i>i</i>[16]</td><td>B1[42]</td><td>B3[42]</td><td>B5[42]</td><td>B7[42]</td><td>B9[42]</td><td>B11[42]</td><td>B13[42]</td><td>B15[42]</td></tr> +<tr><td>LC_<i>i</i>[17]</td><td>B1[43]</td><td>B3[43]</td><td>B5[43]</td><td>B7[43]</td><td>B9[43]</td><td>B11[43]</td><td>B13[43]</td><td>B15[43]</td></tr> +<tr><td>LC_<i>i</i>[18]</td><td>B1[44]</td><td>B3[44]</td><td>B5[44]</td><td>B7[44]</td><td>B9[44]</td><td>B11[44]</td><td>B13[44]</td><td>B15[44]</td></tr> +<tr><td>LC_<i>i</i>[19]</td><td>B1[45]</td><td>B3[45]</td><td>B5[45]</td><td>B7[45]</td><td>B9[45]</td><td>B11[45]</td><td>B13[45]</td><td>B15[45]</td></tr> </table> -</p> <p> -<tt>LC_<i>i</i>[8]</tt> is the <tt>CarryEnable</tt> bit. This bit must be set if the carry logic is used. +<span style="font-family:monospace">LC_<i>i</i>[8]</span> is the <span style="font-family:monospace">CarryEnable</span> bit. This bit must be set if the carry logic is used. </p> <p> -<tt>LC_<i>i</i>[9]</tt> is the <tt>DffEnable</tt> bit. It enables the output flip-flop for the LUT. +<span style="font-family:monospace">LC_<i>i</i>[9]</span> is the <span style="font-family:monospace">DffEnable</span> bit. It enables the output flip-flop for the LUT. </p> <p> -<tt>LC_<i>i</i>[18]</tt> is the <tt>Set_NoReset</tt> bit. When this bit is set then the set/reset signal will set, not reset the flip-flop. +<span style="font-family:monospace">LC_<i>i</i>[18]</span> is the <span style="font-family:monospace">Set_NoReset</span> bit. When this bit is set then the set/reset signal will set, not reset the flip-flop. </p> <p> -<tt>LC_<i>i</i>[19]</tt> is the <tt>AsyncSetReset</tt> bit. When this bit is set then the set/reset signal is asynchronous to the clock. +<span style="font-family:monospace">LC_<i>i</i>[19]</span> is the <span style="font-family:monospace">AsyncSetReset</span> bit. When this bit is set then the set/reset signal is asynchronous to the clock. </p> <p> The LUT implements the following truth table: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>in_3</th><th>in_2</th><th>in_1</th><th>in_0</th><th>out</th></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[4]</tt></td></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[14]</tt></td></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[15]</tt></td></tr> -<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[5]</tt></td></tr> -<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[6]</tt></td></tr> -<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[16]</tt></td></tr> -<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[17]</tt></td></tr> -<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[7]</tt></td></tr> -<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[3]</tt></td></tr> -<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[13]</tt></td></tr> -<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[12]</tt></td></tr> -<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[2]</tt></td></tr> -<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[1]</tt></td></tr> -<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[11]</tt></td></tr> -<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[10]</tt></td></tr> -<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[0]</tt></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[4]</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[14]</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[15]</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[5]</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[6]</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[16]</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[17]</span></td></tr> +<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[7]</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[3]</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[13]</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[12]</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[2]</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[1]</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[11]</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[10]</span></td></tr> +<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[0]</span></td></tr> </table> -</p> <p> LUT inputs that are not connected to anything are driven low. The set/reset @@ -325,3 +319,4 @@ signal is also driven low if not connected to any other driver, and the clock enable signal is driven high when left unconnected. </p> +</body></html> diff --git a/docs/ram_tile.html b/docs/ram_tile.html index 3121f57..73bda8d 100644 --- a/docs/ram_tile.html +++ b/docs/ram_tile.html @@ -1,4 +1,18 @@ +<!DOCTYPE html> +<html><head><meta charset="UTF-8"> +<style> +.ctab { + margin-left: auto; + margin-right: auto; + border: 1px solid gray; +} +.ctab td, .ctab th { + padding: 3px; + border: 1px solid gray; +} +</style> <title>Project IceStorm – RAM Tile Documentation</title> +</head><body> <h1>Project IceStorm – RAM Tile Documentation</h1> <p> @@ -21,75 +35,70 @@ tiles without logic cells in them. A pair or RAM tiles (odd and even y-coordinates) provides an interface to a block ram cell. Like with LOGIC tiles, signals entering the RAM tile have to be routed over local tracks to the block ram inputs. Tiles with odd y-coordinates are "bottom" RAM Tiles (RAMB Tiles), and tiles with even y-coordinates -are "top" RAM Tiles (RAMT Tiles). Each pair of RAMB/RAMT tiles implements a <tt>SB_RAM40_4K</tt> cell. The +are "top" RAM Tiles (RAMT Tiles). Each pair of RAMB/RAMT tiles implements a <span style="font-family:monospace">SB_RAM40_4K</span> cell. The cell ports are spread out over the two tiles as follows: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>SB_RAM40_4K</th><th>RAMB Tile</th><th>RAMT Tile</th></tr> -<tr><td><tt>RDATA[15:0]</tt></td><td><tt>RDATA[7:0]</tt></td><td><tt>RDATA[15:8]</tt></td></tr> -<tr><td><tt>RADDR[10:0]</tt></td><td><tt>-</tt></td><td><tt>RADDR[10:0]</tt></td></tr> -<tr><td><tt>WADDR[10:0]</tt></td><td><tt>WADDR[10:0]</tt></td><td><tt>-</tt></td></tr> -<tr><td><tt>MASK[15:0]</tt></td><td><tt>MASK[7:0]</tt></td><td><tt>MASK[15:8]</tt></td></tr> -<tr><td><tt>WDATA[15:0]</tt></td><td><tt>WDATA[7:0]</tt></td><td><tt>WDATA[15:8]</tt></td></tr> -<tr><td><tt>RCLKE</tt></td><td><tt>-</tt></td><td><tt>RCLKE</tt></td></tr> -<tr><td><tt>RCLK</tt></td><td><tt>-</tt></td><td><tt>RCLK</tt></td></tr> -<tr><td><tt>RE</tt></td><td><tt>-</tt></td><td><tt>RE</tt></td></tr> -<tr><td><tt>WCLKE</tt></td><td><tt>WCLKE</tt></td><td><tt>-</tt></td></tr> -<tr><td><tt>WCLK</tt></td><td><tt>WCLK</tt></td><td><tt>-</tt></td></tr> -<tr><td><tt>WE</tt></td><td><tt>WE</tt></td><td><tt>-</tt></td></tr> +<tr><td><span style="font-family:monospace">RDATA[15:0]</span></td><td><span style="font-family:monospace">RDATA[7:0]</span></td><td><span style="font-family:monospace">RDATA[15:8]</span></td></tr> +<tr><td><span style="font-family:monospace">RADDR[10:0]</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">RADDR[10:0]</span></td></tr> +<tr><td><span style="font-family:monospace">WADDR[10:0]</span></td><td><span style="font-family:monospace">WADDR[10:0]</span></td><td><span style="font-family:monospace">-</span></td></tr> +<tr><td><span style="font-family:monospace">MASK[15:0]</span></td><td><span style="font-family:monospace">MASK[7:0]</span></td><td><span style="font-family:monospace">MASK[15:8]</span></td></tr> +<tr><td><span style="font-family:monospace">WDATA[15:0]</span></td><td><span style="font-family:monospace">WDATA[7:0]</span></td><td><span style="font-family:monospace">WDATA[15:8]</span></td></tr> +<tr><td><span style="font-family:monospace">RCLKE</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">RCLKE</span></td></tr> +<tr><td><span style="font-family:monospace">RCLK</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">RCLK</span></td></tr> +<tr><td><span style="font-family:monospace">RE</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">RE</span></td></tr> +<tr><td><span style="font-family:monospace">WCLKE</span></td><td><span style="font-family:monospace">WCLKE</span></td><td><span style="font-family:monospace">-</span></td></tr> +<tr><td><span style="font-family:monospace">WCLK</span></td><td><span style="font-family:monospace">WCLK</span></td><td><span style="font-family:monospace">-</span></td></tr> +<tr><td><span style="font-family:monospace">WE</span></td><td><span style="font-family:monospace">WE</span></td><td><span style="font-family:monospace">-</span></td></tr> </table> -</p> <p> -The configuration bit <tt>RamConfig PowerUp</tt> in the RAMB tile enables the memory. This bit -is active-low in 1k chips, i.e. an unused RAM block has only this bit set. Note that <tt>icebox_explain.py</tt> -will ignore all RAMB tiles that only have the <tt>RamConfig PowerUp</tt> bit set. +The configuration bit <span style="font-family:monospace">RamConfig PowerUp</span> in the RAMB tile enables the memory. This bit +is active-low in 1k chips, i.e. an unused RAM block has only this bit set. Note that <span style="font-family:monospace">icebox_explain.py</span> +will ignore all RAMB tiles that only have the <span style="font-family:monospace">RamConfig PowerUp</span> bit set. </p> <p> -In 8k chips the <tt>RamConfig PowerUp</tt> bit is active-high. So an unused RAM block has all bits cleared +In 8k chips the <span style="font-family:monospace">RamConfig PowerUp</span> bit is active-high. So an unused RAM block has all bits cleared in the 8k config bitstream. </p> <p> -The <tt>RamConfig CBIT_*</tt> bits in the RAMT tile configure the read/write width of the -memory. Those bits map to the <tt>SB_RAM40_4K</tt> cell parameters as follows: +The <span style="font-family:monospace">RamConfig CBIT_*</span> bits in the RAMT tile configure the read/write width of the +memory. Those bits map to the <span style="font-family:monospace">SB_RAM40_4K</span> cell parameters as follows: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>SB_RAM40_4K</th><th>RAMT Config Bit</th></tr> -<tr><td><tt>WRITE_MODE[0]</tt></td><td><tt>RamConfig CBIT_0</tt></td></tr> -<tr><td><tt>WRITE_MODE[1]</tt></td><td><tt>RamConfig CBIT_1</tt></td></tr> -<tr><td><tt>READ_MODE[0]</tt></td><td><tt>RamConfig CBIT_2</tt></td></tr> -<tr><td><tt>READ_MODE[1]</tt></td><td><tt>RamConfig CBIT_3</tt></td></tr> +<tr><td><span style="font-family:monospace">WRITE_MODE[0]</span></td><td><span style="font-family:monospace">RamConfig CBIT_0</span></td></tr> +<tr><td><span style="font-family:monospace">WRITE_MODE[1]</span></td><td><span style="font-family:monospace">RamConfig CBIT_1</span></td></tr> +<tr><td><span style="font-family:monospace">READ_MODE[0]</span></td><td><span style="font-family:monospace">RamConfig CBIT_2</span></td></tr> +<tr><td><span style="font-family:monospace">READ_MODE[1]</span></td><td><span style="font-family:monospace">RamConfig CBIT_3</span></td></tr> </table> -</p> <p> The read/write mode selects the width of the read/write port: </p> -<p align="center"> -<table cellpadding="3" border> +<table class="ctab"> <tr><th>MODE</th><th>DATA Width</th><th>Used WDATA/RDATA Bits</th></tr> <tr><td>0</td><td>16</td><td>15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0</td></tr> <tr><td>1</td><td>8</td><td>14, 12, 10, 8, 6, 4, 2, 0</td></tr> <tr><td>2</td><td>4</td><td>13, 9, 5, 1</td></tr> <tr><td>3</td><td>2</td><td>11, 3</td></tr> </table> -</p> <p> -The <tt>NegClk</tt> bit in the RAMB tile negates the polarity of the <tt>WCLK</tt> port, -and the <tt>NegClk</tt> bit in the RAMT tile negates the polarity of the <tt>RCLK</tt> port. +The <span style="font-family:monospace">NegClk</span> bit in the RAMB tile negates the polarity of the <span style="font-family:monospace">WCLK</span> port, +and the <span style="font-family:monospace">NegClk</span> bit in the RAMT tile negates the polarity of the <span style="font-family:monospace">RCLK</span> port. </p> <p> A logic tile sends the output of its eight logic cells to its neighbour tiles. A RAM tile does the same thing -with the <tt>RDATA</tt> outputs. Each RAMB tile exports its <tt>RDATA[7:0]</tt> outputs and each RAMT tile -exports its <tt>RDATA[15:8]</tt> outputs via this mechanism. +with the <span style="font-family:monospace">RDATA</span> outputs. Each RAMB tile exports its <span style="font-family:monospace">RDATA[7:0]</span> outputs and each RAMT tile +exports its <span style="font-family:monospace">RDATA[15:8]</span> outputs via this mechanism. </p> +</body></html> diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py index 5488cee..8f07dbc 100644 --- a/icebox/iceboxdb.py +++ b/icebox/iceboxdb.py @@ -705,6 +705,7 @@ B7[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_1 B7[2] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_13 B6[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_5 B6[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_9 +B5[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_10 B4[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_18 B5[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_2 B4[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_26 @@ -750,6 +751,7 @@ B13[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_14 B12[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_22 B12[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_30 B13[2] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_38 +B15[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_46 B13[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_6 B14[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_11 B15[2] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_15 @@ -3939,6 +3941,7 @@ B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 !B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 !B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/RCLK +!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/RE !B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 !B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 !B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 @@ -3968,6 +3971,7 @@ B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 !B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK +B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/RCLKE B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 @@ -5399,6 +5403,7 @@ B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK !B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 !B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK diff --git a/icefuzz/.gitignore b/icefuzz/.gitignore index 4406a27..e32cfc1 100644 --- a/icefuzz/.gitignore +++ b/icefuzz/.gitignore @@ -4,5 +4,6 @@ *.tmp/ *.txt *.vsb +*.sdf /work_*/ __pycache__ diff --git a/icefuzz/Makefile b/icefuzz/Makefile index 030eb35..0233eb4 100644 --- a/icefuzz/Makefile +++ b/icefuzz/Makefile @@ -36,6 +36,24 @@ endif diff -U0 cached_ramb_8k.txt bitdata_ramb_8k.txt || cp -v bitdata_ramb_8k.txt cached_ramb_8k.txt diff -U0 cached_ramt_8k.txt bitdata_ramt_8k.txt || cp -v bitdata_ramt_8k.txt cached_ramt_8k.txt +timings: +ifeq ($(EIGTHK),_8k) + cp tmedges_8k.txt tmedges.tmp + for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done + sort -u tmedges.tmp > tmedges_8k.txt && rm -f tmedges.tmp + python3 timings.py -t timings_8k.txt work_*/*.sdf > timings_8k.new + mv timings_8k.new timings_8k.txt +else + cp tmedges_1k.txt tmedges.tmp + for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done + sort -u tmedges.tmp > tmedges_1k.txt && rm -f tmedges.tmp + python3 timings.py -t timings_1k.txt work_*/*.sdf > timings_1k.new + mv timings_1k.new timings_1k.txt +endif + +timings_html: + python3 timings.py -h tmedges_1k.txt -t timings_1k.txt -l "HX1K with default temp/volt settings" > timings_1k.html + data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(EIGTHK).txt cached_ramt$(EIGTHK).txt gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new gawk '{ print "logic", $$0; }' cached_logic.txt >> data_cached.new @@ -64,11 +82,11 @@ define data_template data_$(1).txt: make_$(1).py ../icepack/icepack ifeq ($(EIGTHK),_8k) ICE8KPINS=1 python3 make_$(1).py - ICEDEV=hx8k-ct256 $(MAKE) -C work_$(1) + +ICEDEV=hx8k-ct256 $(MAKE) -C work_$(1) python3 extract.py -8 work_$(1)/*.glb > $$@ else python3 make_$(1).py - $(MAKE) -C work_$(1) + +$(MAKE) -C work_$(1) python3 extract.py work_$(1)/*.glb > $$@ endif endef diff --git a/icefuzz/cached_io.txt b/icefuzz/cached_io.txt index 257e8d0..6033a28 100644 --- a/icefuzz/cached_io.txt +++ b/icefuzz/cached_io.txt @@ -12,6 +12,7 @@ (0 13) Enable bit of Mux _out_links/OutMux0_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_6 (0 14) Enable bit of Mux _out_links/OutMux7_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_r_7 (0 14) Enable bit of Mux _out_links/OutMux7_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_b_7 +(0 15) Enable bit of Mux _out_links/OutMux5_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_46 (0 15) Enable bit of Mux _out_links/OutMux5_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_46 (0 2) Enable bit of Mux _out_links/OutMux7_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_4 (0 2) Enable bit of Mux _out_links/OutMux7_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_4 @@ -52,6 +53,7 @@ (1 4) Enable bit of Mux _out_links/OutMux3_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_26 (1 4) Enable bit of Mux _out_links/OutMux3_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_26 (1 5) Enable bit of Mux _out_links/OutMux1_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_10 +(1 5) Enable bit of Mux _out_links/OutMux1_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_10 (1 6) Enable bit of Mux _out_links/OutMux8_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_9 (1 6) Enable bit of Mux _out_links/OutMux8_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_9 (1 7) Enable bit of Mux _out_links/OutMux6_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_1 diff --git a/icefuzz/cached_ramb_8k.txt b/icefuzz/cached_ramb_8k.txt index 843ce53..b19db9a 100644 --- a/icefuzz/cached_ramb_8k.txt +++ b/icefuzz/cached_ramb_8k.txt @@ -57,6 +57,7 @@ (0 8) routing glb_netwk_7 <X> glb2local_1 (0 9) routing glb_netwk_1 <X> glb2local_1 (0 9) routing glb_netwk_3 <X> glb2local_1 +(0 9) routing glb_netwk_5 <X> glb2local_1 (0 9) routing glb_netwk_7 <X> glb2local_1 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 @@ -128,9 +129,11 @@ (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 (1 9) routing glb_netwk_4 <X> glb2local_1 +(1 9) routing glb_netwk_5 <X> glb2local_1 (1 9) routing glb_netwk_6 <X> glb2local_1 (1 9) routing glb_netwk_7 <X> glb2local_1 (10 0) routing sp4_h_l_40 <X> sp4_h_r_1 diff --git a/icefuzz/cached_ramt.txt b/icefuzz/cached_ramt.txt index c51dafa..84c2126 100644 --- a/icefuzz/cached_ramt.txt +++ b/icefuzz/cached_ramt.txt @@ -35,6 +35,7 @@ (0 3) routing glb_netwk_7 <X> wire_bram/ram/RCLK (0 3) routing lc_trk_g1_1 <X> wire_bram/ram/RCLK (0 3) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK +(0 4) routing glb_netwk_5 <X> wire_bram/ram/RCLKE (0 4) routing glb_netwk_7 <X> wire_bram/ram/RCLKE (0 4) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE (0 4) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE @@ -82,6 +83,7 @@ (1 13) routing glb_netwk_5 <X> glb2local_3 (1 13) routing glb_netwk_6 <X> glb2local_3 (1 13) routing glb_netwk_7 <X> glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE @@ -100,6 +102,7 @@ (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17 (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/RCLKE +(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE diff --git a/icefuzz/database.py b/icefuzz/database.py index 7720ce2..9f0ebc9 100644 --- a/icefuzz/database.py +++ b/icefuzz/database.py @@ -2,12 +2,9 @@ import re, sys, os -def cmp_bits(a, b): +def sort_bits_key(a): if a[0] == "!": a = a[1:] - if b[0] == "!": b = b[1:] - a = re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), a) - b = re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), b) - return cmp(a, b) + return re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), a) def read_database(filename, tile_type): raw_db = list() @@ -107,7 +104,7 @@ def read_database(filename, tile_type): database = list() for func in sorted(func_to_bits): bits = func_to_bits[func] - entry = (",".join(sorted(bits, cmp_bits)),) + func + entry = (",".join(sorted(bits, key=sort_bits_key)),) + func database.append(entry) return database diff --git a/icefuzz/icecube.sh b/icefuzz/icecube.sh index 54421a4..f3dabc6 100644 --- a/icefuzz/icecube.sh +++ b/icefuzz/icecube.sh @@ -189,5 +189,6 @@ cp "$1.tmp"/outputs/bitmap/top_bitmap.bin "$1.bin" cp "$1.tmp"/outputs/bitmap/top_bitmap_glb.txt "$1.glb" cp "$1.tmp"/outputs/placer/top_sbt.pcf "$1.psb" cp "$1.tmp"/outputs/netlist/top_sbt.v "$1.vsb" +cp "$1.tmp"/outputs/netlist/top_sbt.sdf "$1.sdf" $scriptdir/../icepack/iceunpack "$1.bin" "$1.txt" diff --git a/icefuzz/timings.py b/icefuzz/timings.py new file mode 100644 index 0000000..75215d5 --- /dev/null +++ b/icefuzz/timings.py @@ -0,0 +1,437 @@ +#!/usr/bin/env python3 + +import getopt, sys, re + +ignore_cells = set([ + "ADTTRIBUF", "CascadeBuf", "DL", "GIOBUG", "LUT_MUX", "MUX4", + "PLL40_2_FEEDBACK_PATH_DELAY", "PLL40_2_FEEDBACK_PATH_EXTERNAL", + "PLL40_2_FEEDBACK_PATH_PHASE_AND_DELAY", "PLL40_2_FEEDBACK_PATH_SIMPLE", + "PLL40_2F_FEEDBACK_PATH_DELAY", "PLL40_2F_FEEDBACK_PATH_EXTERNAL", + "PLL40_2F_FEEDBACK_PATH_PHASE_AND_DELAY", "PLL40_2F_FEEDBACK_PATH_SIMPLE", + "PLL40_FEEDBACK_PATH_DELAY", "PLL40_FEEDBACK_PATH_EXTERNAL", + "PLL40_FEEDBACK_PATH_PHASE_AND_DELAY", "PLL40_FEEDBACK_PATH_SIMPLE", + "PRE_IO_PIN_TYPE", "sync_clk_enable", "TRIBUF" +]) + +database = dict() +sdf_inputs = list() +txt_inputs = list() +output_mode = "txt" +label = "unknown" +edgefile = None + +def usage(): + print(""" +Usage: python3 timings.py [options] [sdf_file..] + + -t filename + read TXT file + + -l label + label for HTML file title + + -h edgefile + output HTML, use specified edge file + + -s + output SDF (not TXT) format +""") + sys.exit(0) + + +try: + opts, args = getopt.getopt(sys.argv[1:], "t:l:h:s") +except: + usage() + +for o, a in opts: + if o == "-t": + txt_inputs.append(a) + elif o == "-l": + label = a + elif o == "-h": + output_mode = "html" + edgefile = a + elif o == "-s": + output_mode = "sdf" + else: + usage() + +sdf_inputs += args + + +convert = lambda text: int(text) if text.isdigit() else text.lower() +alphanum_key = lambda key: [ convert(c) for c in re.split('([0-9]+)', key) ] +alphanum_key_list = lambda l: [len(l)] + [ alphanum_key(s) for s in l ] + + +def skip_whitespace(text, cursor): + while cursor < len(text) and text[cursor] in [" ", "\t", "\r", "\n"]: + cursor += 1 + return cursor + + +def parse_sdf(text, cursor): + cursor = skip_whitespace(text, cursor) + + if cursor < len(text) and text[cursor] == "(": + expr = [] + cursor += 1 + while cursor < len(text) and text[cursor] != ")": + child, cursor = parse_sdf(text, cursor) + expr.append(child) + cursor = skip_whitespace(text, cursor) + return expr, cursor+1 + + if cursor < len(text) and text[cursor] == '"': + expr = '"' + cursor += 1 + while cursor < len(text) and text[cursor] != '"': + expr += text[cursor] + cursor += 1 + return expr + '"', cursor+1 + + expr = "" + while cursor < len(text) and text[cursor] not in [" ", "\t", "\r", "\n", "(", ")"]: + expr += text[cursor] + cursor += 1 + return expr, cursor + + +def sdf_to_string(expr): + if type(expr) is list: + tokens = [] + tokens.append("(") + first_child = True + for child in expr: + if not first_child: + tokens.append(" ") + tokens.append(sdf_to_string(child)) + first_child = False + tokens.append(")") + return "".join(tokens) + else: + return expr + + +def dump_sdf(expr, indent=""): + if type(expr) is list: + if len(expr) > 0 and expr[0] in ["IOPATH", "SETUP", "HOLD", "CELLTYPE", "INSTANCE", "SDFVERSION", + "DESIGN", "DATE", "VENDOR", "DIVIDER", "TIMESCALE", "RECOVERY", "REMOVAL"]: + print(indent + sdf_to_string(expr)) + else: + print("%s(%s" % (indent, expr[0] if len(expr) > 0 else "")) + for child in expr[1:]: + dump_sdf(child, indent + " ") + print("%s)" % indent) + else: + print("%s%s" % (indent, expr)) + + +def generalize_instances(expr): + if type(expr) is list: + if len(expr) == 2 and expr[0] == "INSTANCE": + expr[1] = "*" + for child in expr: + generalize_instances(child) + + +def list_to_tuple(expr): + if type(expr) is list: + tup = [] + for child in expr: + tup.append(list_to_tuple(child)) + return tuple(tup) + return expr + + +def uniquify_cells(expr): + cache = set() + filtered_expr = [] + + for child in expr: + t = list_to_tuple(child) + if t not in cache: + filtered_expr.append(child) + cache.add(t) + + return filtered_expr + + +def rewrite_celltype(celltype): + if celltype.startswith("PRE_IO_PIN_TYPE_"): + celltype = "PRE_IO_PIN_TYPE" + + if celltype.startswith("Span4Mux"): + if celltype == "Span4Mux": + celltype = "Span4Mux_v4" + elif celltype == "Span4Mux_v": + celltype = "Span4Mux_v4" + elif celltype == "Span4Mux_h": + celltype = "Span4Mux_h4" + else: + match = re.match("Span4Mux_s(.*)_(h|v)", celltype) + if match: + celltype = "Span4Mux_%c%d" % (match.group(2), int(match.group(1))) + + if celltype.startswith("Span12Mux"): + if celltype == "Span12Mux": + celltype = "Span12Mux_v12" + elif celltype == "Span12Mux_v": + celltype = "Span12Mux_v12" + elif celltype == "Span12Mux_h": + celltype = "Span12Mux_h12" + else: + match = re.match("Span12Mux_s(.*)_(h|v)", celltype) + if match: + celltype = "Span12Mux_%c%d" % (match.group(2), int(match.group(1))) + + return celltype + + +def add_entry(celltype, entry): + entry = sdf_to_string(entry) + entry = entry.replace("(posedge ", "posedge:") + entry = entry.replace("(negedge ", "negedge:") + entry = entry.replace("(", "") + entry = entry.replace(")", "") + entry = entry.split() + if celltype.count("FEEDBACK") == 0 and entry[0] == "IOPATH" and entry[2].startswith("PLLOUT"): + entry[3] = "*:*:*" + entry[4] = "*:*:*" + database[celltype].add(tuple(entry)) + + +########################################### +# Parse SDF input files + +for filename in sdf_inputs: + print("### reading SDF file %s" % filename, file=sys.stderr) + + intext = [] + with open(filename, "r") as f: + for line in f: + line = re.sub("//.*", "", line) + intext.append(line) + + sdfdata, _ = parse_sdf("".join(intext), 0) + generalize_instances(sdfdata) + sdfdata = uniquify_cells(sdfdata) + + for cell in sdfdata: + if cell[0] != "CELL": + continue + + celltype = None + + for stmt in cell: + if stmt[0] == "CELLTYPE": + celltype = rewrite_celltype(stmt[1][1:-1]) + database.setdefault(celltype, set()) + + if stmt[0] == "DELAY": + assert stmt[1][0] == "ABSOLUTE" + for entry in stmt[1][1:]: + assert entry[0] == "IOPATH" + add_entry(celltype, entry) + + if stmt[0] == "TIMINGCHECK": + for entry in stmt[1:]: + add_entry(celltype, entry) + + +########################################### +# Parse TXT input files + +for filename in txt_inputs: + print("### reading TXT file %s" % filename, file=sys.stderr) + with open(filename, "r") as f: + celltype = None + for line in f: + line = line.split() + if len(line) > 1: + if line[0] == "CELL": + celltype = rewrite_celltype(line[1]) + database.setdefault(celltype, set()) + else: + add_entry(celltype, line) + + +########################################### +# Filter database + +for celltype in ignore_cells: + del database[celltype] + + +########################################### +# Create SDF output + +if output_mode == "sdf": + print("(DELAYFILE") + print(" (SDFVERSION \"3.0\")") + print(" (TIMESCALE 1ps)") + + def format_entry(entry): + text = [] + for i in range(len(entry)): + if i > 2: + text.append("(%s)" % entry[i]) + elif entry[i].startswith("posedge:"): + text.append("(posedge %s)" % entry[i].replace("posedge:", "")) + elif entry[i].startswith("negedge:"): + text.append("(negedge %s)" % entry[i].replace("negedge:", "")) + else: + text.append(entry[i]) + return " ".join(text) + + for celltype in sorted(database, key=alphanum_key): + print(" (CELL") + print(" (CELLTYPE \"%s\")" % celltype) + print(" (INSTANCE *)") + + delay_abs_entries = list() + timingcheck_entries = list() + for entry in sorted(database[celltype], key=alphanum_key_list): + if entry[0] == "IOPATH": + delay_abs_entries.append(entry) + else: + timingcheck_entries.append(entry) + + if len(delay_abs_entries) != 0: + print(" (DELAY") + print(" (ABSOLUTE") + for entry in delay_abs_entries: + print(" (%s)" % format_entry(entry)) + print(" )") + print(" )") + + if len(timingcheck_entries) != 0: + print(" (TIMINGCHECK") + for entry in timingcheck_entries: + print(" (%s)" % format_entry(entry)) + print(" )") + + print(" )") + + print(")") + + +########################################### +# Create TXT output + +if output_mode == "txt": + for celltype in sorted(database, key=alphanum_key): + print("CELL %s" % celltype) + entries_lens = list() + for entry in database[celltype]: + for i in range(len(entry)): + if i < len(entries_lens): + entries_lens[i] = max(entries_lens[i], len(entry[i])) + else: + entries_lens.append(len(entry[i])) + for entry in sorted(database[celltype], key=alphanum_key_list): + for i in range(len(entry)): + print("%s%-*s" % (" " if i != 0 else "", entries_lens[i] if i != len(entry)-1 else 0, entry[i]), end="") + print() + print() + + +########################################### +# Create HTML output + +if output_mode == "html": + print("<h1>IceStorm Timing Model: %s</h1>" % label) + + edge_celltypes = set() + source_by_sink_desc = dict() + sink_by_source_desc = dict() + + with open(edgefile, "r") as f: + for line in f: + source, sink = line.split() + source_cell, source_port = source.split(".") + sink_cell, sink_port = sink.split(".") + + source_cell = rewrite_celltype(source_cell) + sink_cell = rewrite_celltype(sink_cell) + + assert source_cell not in ignore_cells + assert sink_cell not in ignore_cells + + if source_cell in ["GND", "VCC"]: + continue + + source_by_sink_desc.setdefault(sink_cell, set()) + sink_by_source_desc.setdefault(source_cell, set()) + + source_by_sink_desc[sink_cell].add((sink_port, source_cell, source_port)) + sink_by_source_desc[source_cell].add((source_port, sink_cell, sink_port)) + + edge_celltypes.add(source_cell) + edge_celltypes.add(sink_cell) + + print("<div style=\"-webkit-column-count: 3; -moz-column-count: 3; column-count: 3;\"><ul style=\"margin:0\">") + for celltype in sorted(database, key=alphanum_key): + if celltype not in edge_celltypes: + print("### ignoring unused cell type %s" % celltype, file=sys.stderr) + else: + print("<li><a href=\"#%s\">%s</a></li>" % (celltype, celltype)) + print("</ul></div>") + + for celltype in sorted(database, key=alphanum_key): + if celltype not in edge_celltypes: + continue + + print("<p><hr></p>") + print("<h2><a name=\"%s\">%s</a></h2>" % (celltype, celltype)) + + if celltype in source_by_sink_desc: + print("<h3>Sources driving this cell type:</h3>") + print("<table width=\"600\" border>") + print("<tr><th>Input Port</th><th>Source Cell</th><th>Source Port</th></tr>") + for entry in sorted(source_by_sink_desc[celltype], key=alphanum_key_list): + print("<tr><td>%s</td><td><a href=\"#%s\">%s</a></td><td>%s</td></tr>" % (entry[0], entry[1], entry[1], entry[2])) + print("</table>") + + if celltype in sink_by_source_desc: + print("<h3>Sinks driven by this cell type:</h3>") + print("<table width=\"600\" border>") + print("<tr><th>Output Port</th><th>Sink Cell</th><th>Sink Port</th></tr>") + for entry in sorted(sink_by_source_desc[celltype], key=alphanum_key_list): + print("<tr><td>%s</td><td><a href=\"#%s\">%s</a></td><td>%s</td></tr>" % (entry[0], entry[1], entry[1], entry[2])) + print("</table>") + + delay_abs_entries = list() + timingcheck_entries = list() + for entry in sorted(database[celltype], key=alphanum_key_list): + if entry[0] == "IOPATH": + delay_abs_entries.append(entry) + else: + timingcheck_entries.append(entry) + + if len(delay_abs_entries) > 0: + print("<h3>Propagation Delays:</h3>") + print("<table width=\"800\" border>") + print("<tr><th rowspan=\"2\">Input Port</th><th rowspan=\"2\">Output Port</th>") + print("<th colspan=\"3\">Low-High Transition</th><th colspan=\"3\">High-Low Transition</th></tr>") + print("<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>") + for entry in delay_abs_entries: + print("<tr><td>%s</td><td>%s</td>" % (entry[1].replace(":", " "), entry[2].replace(":", " ")), end="") + print("<td>%s</td><td>%s</td><td>%s</td>" % tuple(entry[3].split(":")), end="") + print("<td>%s</td><td>%s</td><td>%s</td>" % tuple(entry[4].split(":")), end="") + print("</tr>") + print("</table>") + + if len(timingcheck_entries) > 0: + print("<h3>Timing Checks:</h3>") + print("<table width=\"800\" border>") + print("<tr><th rowspan=\"2\">Check Type</th><th rowspan=\"2\">Input Port</th>") + print("<th rowspan=\"2\">Output Port</th><th colspan=\"3\">Timing</th></tr>") + print("<tr><th>Min</th><th>Typ</th><th>Max</th></tr>") + for entry in timingcheck_entries: + print("<tr><td>%s</td><td>%s</td><td>%s</td>" % (entry[0], entry[1].replace(":", " "), entry[2].replace(":", " ")), end="") + print("<td>%s</td><td>%s</td><td>%s</td>" % tuple(entry[3].split(":")), end="") + print("</tr>") + print("</table>") + diff --git a/icefuzz/timings_1k.txt b/icefuzz/timings_1k.txt new file mode 100644 index 0000000..11b3b39 --- /dev/null +++ b/icefuzz/timings_1k.txt @@ -0,0 +1,528 @@ +CELL CascadeMux +IOPATH I O 0:0:0 0:0:0 + +CELL CEMux +IOPATH I O 562.692:731:888.975 516.892:671.5:816.617 + +CELL ClkMux +IOPATH I O 287.889:374:454.825 215.917:280.5:341.118 + +CELL gio2CtrlBuf +IOPATH I O 0:0:0 0:0:0 + +CELL Glb2LocalMux +IOPATH I O 418.748:544:661.563 333.689:433.5:527.183 + +CELL GlobalMux +IOPATH I O 143.944:187:227.412 71.9722:93.5:113.706 + +CELL ICE_CARRY_IN_MUX +IOPATH carryinitin carryinitout 183.202:238:289.434 163.573:212.5:258.423 + +CELL ICE_GB +IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 575.778:748:909.649 523.434:680:826.954 + +CELL InMux +IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445 + +CELL INV +IOPATH I O 0:0:0 0:0:0 + +CELL IO_PAD +IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 +IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990 +IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942 +IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 +IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540 + +CELL IoInMux +IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445 + +CELL IoSpan4Mux +IOPATH I O 268.26:348.5:423.814 300.975:391:475.498 + +CELL LocalMux +IOPATH I O 307.518:399.5:485.835 287.889:374:454.825 + +CELL LogicCell40 +HOLD negedge:ce posedge:clk 0:0:0 +HOLD negedge:in0 posedge:clk 0:0:0 +HOLD negedge:in1 posedge:clk 0:0:0 +HOLD negedge:in2 posedge:clk 0:0:0 +HOLD negedge:in3 posedge:clk 0:0:0 +HOLD negedge:sr posedge:clk -184.184:-239.275:-290.984 +HOLD posedge:ce posedge:clk 0:0:0 +HOLD posedge:in0 posedge:clk 0:0:0 +HOLD posedge:in1 posedge:clk 0:0:0 +HOLD posedge:in2 posedge:clk 0:0:0 +HOLD posedge:in3 posedge:clk 0:0:0 +HOLD posedge:sr posedge:clk -167.106:-217.09:-264.005 +RECOVERY negedge:sr posedge:clk 148.983:193.545:235.372 +RECOVERY posedge:sr posedge:clk 0:0:0 +REMOVAL negedge:sr posedge:clk 0:0:0 +REMOVAL posedge:sr posedge:clk 0:0:0 +SETUP negedge:ce posedge:clk 0:0:0 +SETUP negedge:in0 posedge:clk 372.947:484.5:589.205 +SETUP negedge:in1 posedge:clk 353.318:459:558.194 +SETUP negedge:in2 posedge:clk 300.975:391:475.498 +SETUP negedge:in3 posedge:clk 202.831:263.5:320.445 +SETUP negedge:sr posedge:clk 130.859:170:206.738 +SETUP posedge:ce posedge:clk 0:0:0 +SETUP posedge:in0 posedge:clk 438.376:569.5:692.574 +SETUP posedge:in1 posedge:clk 372.947:484.5:589.205 +SETUP posedge:in2 posedge:clk 346.775:450.5:547.857 +SETUP posedge:in3 posedge:clk 255.174:331.5:403.14 +SETUP posedge:sr posedge:clk 189.745:246.5:299.771 +IOPATH carryin carryout 117.773:153:186.065 98.144:127.5:155.054 +IOPATH in0 lcout 418.748:544:661.563 359.861:467.5:568.531 +IOPATH in0 ltout 340.232:442:537.52 359.861:467.5:568.531 +IOPATH in1 carryout 242.088:314.5:382.466 229.003:297.5:361.792 +IOPATH in1 lcout 372.947:484.5:589.205 353.318:459:558.194 +IOPATH in1 ltout 300.975:391:475.498 353.318:459:558.194 +IOPATH in2 carryout 215.917:280.5:341.118 124.316:161.5:196.402 +IOPATH in2 lcout 353.318:459:558.194 327.147:425:516.846 +IOPATH in2 ltout 287.889:374:454.825 320.604:416.5:506.509 +IOPATH in3 lcout 294.432:382.5:465.161 268.26:348.5:423.814 +IOPATH in3 ltout 248.631:323:392.803 255.174:331.5:403.14 +IOPATH posedge:clk lcout 503.806:654.5:795.943 503.806:654.5:795.943 +IOPATH sr lcout 0:0:0 558.989:726.189:883.125 +IOPATH sr lcout 558.963:726.155:883.083 0:0:0 + +CELL Odrv4 +IOPATH I O 327.147:425:516.846 346.775:450.5:547.857 + +CELL Odrv12 +IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 + +CELL PLL40 +IOPATH PLLIN PLLOUTCORE *:*:* *:*:* +IOPATH PLLIN PLLOUTGLOBAL *:*:* *:*:* + +CELL PLL40_2 +IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* +IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* +IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* +IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* + +CELL PLL40_2F +IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* +IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* +IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* +IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* + +CELL PRE_IO +HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 +HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 +HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0 +HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0 +HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 +HOLD negedge:PADIN negedge:INPUTCLK 0:0:0 +HOLD negedge:PADIN posedge:INPUTCLK 0:0:0 +HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 +HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 +HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0 +HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0 +HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 +HOLD posedge:PADIN negedge:INPUTCLK 0:0:0 +HOLD posedge:PADIN posedge:INPUTCLK 0:0:0 +SETUP negedge:CLOCKENABLE posedge:INPUTCLK 65.4293:85:103.369 +SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 65.4293:85:103.369 +SETUP negedge:DOUT0 posedge:OUTPUTCLK 65.4293:85:103.369 +SETUP negedge:DOUT1 negedge:OUTPUTCLK 65.4293:85:103.369 +SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 65.4293:85:103.369 +SETUP negedge:PADIN negedge:INPUTCLK 1527.97:1985:2413.98 +SETUP negedge:PADIN posedge:INPUTCLK 1527.97:1985:2413.98 +SETUP posedge:CLOCKENABLE posedge:INPUTCLK 71.9722:93.5:113.706 +SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706 +SETUP posedge:DOUT0 posedge:OUTPUTCLK 71.9722:93.5:113.706 +SETUP posedge:DOUT1 negedge:OUTPUTCLK 71.9722:93.5:113.706 +SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706 +SETUP posedge:PADIN negedge:INPUTCLK 1534.51:1993.5:2424.32 +SETUP posedge:PADIN posedge:INPUTCLK 1534.51:1993.5:2424.32 +IOPATH DOUT0 PADOUT 1871.28:2431:2956.36 2087.19:2711.5:3297.48 +IOPATH LATCHINPUTVALUE DIN0 320.604:416.5:506.509 346.775:450.5:547.857 +IOPATH negedge:INPUTCLK DIN1 130.859:170:206.738 130.859:170:206.738 +IOPATH negedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738 +IOPATH OUTPUTENABLE PADOEN 163.573:212.5:258.423 196.288:255:310.108 +IOPATH PADIN DIN0 575.778:748:909.649 431.833:561:682.237 +IOPATH posedge:INPUTCLK DIN0 130.859:170:206.738 130.859:170:206.738 +IOPATH posedge:OUTPUTCLK PADOEN 104.687:136:165.391 130.859:170:206.738 +IOPATH posedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738 + +CELL PRE_IO_GBUF +IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1313.95:1706.97:2075.86 1170.01:1519.97:1848.45 + +CELL SB_PLL40_2F_CORE +IOPATH REFERENCECLK PLLOUTCOREA *:*:* *:*:* +IOPATH REFERENCECLK PLLOUTCOREB *:*:* *:*:* +IOPATH REFERENCECLK PLLOUTGLOBALA *:*:* *:*:* +IOPATH REFERENCECLK PLLOUTGLOBALB *:*:* *:*:* + +CELL SB_PLL40_CORE +IOPATH REFERENCECLK PLLOUTCORE *:*:* *:*:* +IOPATH REFERENCECLK PLLOUTGLOBAL *:*:* *:*:* + +CELL SB_RAM40_4K +HOLD negedge:MASK[0] posedge:WCLK 0:0:0 +HOLD negedge:MASK[1] posedge:WCLK 0:0:0 +HOLD negedge:MASK[2] posedge:WCLK 0:0:0 +HOLD negedge:MASK[3] posedge:WCLK 0:0:0 +HOLD negedge:MASK[4] posedge:WCLK 0:0:0 +HOLD negedge:MASK[5] posedge:WCLK 0:0:0 +HOLD negedge:MASK[6] posedge:WCLK 0:0:0 +HOLD negedge:MASK[7] posedge:WCLK 0:0:0 +HOLD negedge:MASK[8] posedge:WCLK 0:0:0 +HOLD negedge:MASK[9] posedge:WCLK 0:0:0 +HOLD negedge:MASK[10] posedge:WCLK 0:0:0 +HOLD negedge:MASK[11] posedge:WCLK 0:0:0 +HOLD negedge:MASK[12] posedge:WCLK 0:0:0 +HOLD negedge:MASK[13] posedge:WCLK 0:0:0 +HOLD negedge:MASK[14] posedge:WCLK 0:0:0 +HOLD negedge:MASK[15] posedge:WCLK 0:0:0 +HOLD negedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RCLKE posedge:RCLK 49.072:63.75:77.5269 +HOLD negedge:RE posedge:RCLK 78.5152:102:124.043 +HOLD negedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WCLKE posedge:WCLK 25.5174:33.15:40.314 +HOLD negedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WE posedge:WCLK 45.8005:59.5:72.3585 +HOLD posedge:MASK[0] posedge:WCLK 0:0:0 +HOLD posedge:MASK[1] posedge:WCLK 0:0:0 +HOLD posedge:MASK[2] posedge:WCLK 0:0:0 +HOLD posedge:MASK[3] posedge:WCLK 0:0:0 +HOLD posedge:MASK[4] posedge:WCLK 0:0:0 +HOLD posedge:MASK[5] posedge:WCLK 0:0:0 +HOLD posedge:MASK[6] posedge:WCLK 0:0:0 +HOLD posedge:MASK[7] posedge:WCLK 0:0:0 +HOLD posedge:MASK[8] posedge:WCLK 0:0:0 +HOLD posedge:MASK[9] posedge:WCLK 0:0:0 +HOLD posedge:MASK[10] posedge:WCLK 0:0:0 +HOLD posedge:MASK[11] posedge:WCLK 0:0:0 +HOLD posedge:MASK[12] posedge:WCLK 0:0:0 +HOLD posedge:MASK[13] posedge:WCLK 0:0:0 +HOLD posedge:MASK[14] posedge:WCLK 0:0:0 +HOLD posedge:MASK[15] posedge:WCLK 0:0:0 +HOLD posedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RCLKE posedge:RCLK 49.072:63.75:77.5269 +HOLD posedge:RE posedge:RCLK 78.5152:102:124.043 +HOLD posedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WCLKE posedge:WCLK 25.5174:33.15:40.314 +HOLD posedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WE posedge:WCLK 45.8005:59.5:72.3585 +SETUP negedge:MASK[0] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[1] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[2] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[3] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[4] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[5] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[6] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[7] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[8] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[9] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[10] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[11] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[12] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[13] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[14] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[15] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RCLKE posedge:RCLK 248.631:323:392.803 +SETUP negedge:RE posedge:RCLK 91.601:119:144.717 +SETUP negedge:WADDR[0] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[1] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[2] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[3] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[4] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[5] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[6] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[7] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[8] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[9] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[10] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WCLKE posedge:WCLK 248.631:323:392.803 +SETUP negedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WE posedge:WCLK 124.316:161.5:196.402 +SETUP posedge:MASK[0] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[1] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[2] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[3] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[4] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[5] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[6] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[7] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[8] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[9] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[10] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[11] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[12] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[13] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[14] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[15] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RCLKE posedge:RCLK 248.631:323:392.803 +SETUP posedge:RE posedge:RCLK 91.601:119:144.717 +SETUP posedge:WADDR[0] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[1] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[2] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[3] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[4] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[5] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[6] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[7] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[8] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[9] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[10] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WCLKE posedge:WCLK 248.631:323:392.803 +SETUP posedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WE posedge:WCLK 124.316:161.5:196.402 +IOPATH posedge:RCLK RDATA[0] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[1] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[2] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[3] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[4] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[5] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[6] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[7] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[8] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[9] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[10] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[11] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[12] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[13] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[14] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[15] 2002.14:2601:3163.1 2002.14:2601:3163.1 + +CELL Sp12to4 +IOPATH I O 399.119:518.5:630.552 418.748:544:661.563 + +CELL Span4Mux_h0 +IOPATH I O 137.402:178.5:217.075 130.859:170:206.738 + +CELL Span4Mux_h1 +IOPATH I O 163.573:212.5:258.423 157.03:204:248.086 + +CELL Span4Mux_h2 +IOPATH I O 189.745:246.5:299.771 189.745:246.5:299.771 + +CELL Span4Mux_h3 +IOPATH I O 215.917:280.5:341.118 215.917:280.5:341.118 + +CELL Span4Mux_h4 +IOPATH I O 281.346:365.5:444.488 294.432:382.5:465.161 + +CELL Span4Mux_v0 +IOPATH I O 189.745:246.5:299.771 176.659:229.5:279.097 + +CELL Span4Mux_v1 +IOPATH I O 189.745:246.5:299.771 183.202:238:289.434 + +CELL Span4Mux_v2 +IOPATH I O 235.546:306:372.129 235.546:306:372.129 + +CELL Span4Mux_v3 +IOPATH I O 294.432:382.5:465.161 314.061:408:496.172 + +CELL Span4Mux_v4 +IOPATH I O 327.147:425:516.846 346.775:450.5:547.857 + +CELL Span12Mux_h0 +IOPATH I O 130.859:170:206.738 137.402:178.5:217.075 + +CELL Span12Mux_h1 +IOPATH I O 124.316:161.5:196.402 124.316:161.5:196.402 + +CELL Span12Mux_h2 +IOPATH I O 150.487:195.5:237.749 157.03:204:248.086 + +CELL Span12Mux_h3 +IOPATH I O 157.03:204:248.086 170.116:221:268.76 + +CELL Span12Mux_h4 +IOPATH I O 183.202:238:289.434 202.831:263.5:320.445 + +CELL Span12Mux_h5 +IOPATH I O 215.917:280.5:341.118 242.088:314.5:382.466 + +CELL Span12Mux_h6 +IOPATH I O 235.546:306:372.129 261.717:340:413.477 + +CELL Span12Mux_h7 +IOPATH I O 268.26:348.5:423.814 300.975:391:475.498 + +CELL Span12Mux_h8 +IOPATH I O 320.604:416.5:506.509 359.861:467.5:568.531 + +CELL Span12Mux_h9 +IOPATH I O 366.404:476:578.868 405.662:527:640.889 + +CELL Span12Mux_h10 +IOPATH I O 399.119:518.5:630.552 438.376:569.5:692.574 + +CELL Span12Mux_h11 +IOPATH I O 438.376:569.5:692.574 490.72:637.5:775.269 + +CELL Span12Mux_h12 +IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 + +CELL Span12Mux_v0 +IOPATH I O 91.601:119:144.717 98.144:127.5:155.054 + +CELL Span12Mux_v1 +IOPATH I O 98.144:127.5:155.054 98.144:127.5:155.054 + +CELL Span12Mux_v2 +IOPATH I O 130.859:170:206.738 143.944:187:227.412 + +CELL Span12Mux_v3 +IOPATH I O 137.402:178.5:217.075 157.03:204:248.086 + +CELL Span12Mux_v4 +IOPATH I O 170.116:221:268.76 196.288:255:310.108 + +CELL Span12Mux_v5 +IOPATH I O 222.46:289:351.455 248.631:323:392.803 + +CELL Span12Mux_v6 +IOPATH I O 242.088:314.5:382.466 268.26:348.5:423.814 + +CELL Span12Mux_v7 +IOPATH I O 261.717:340:413.477 294.432:382.5:465.161 + +CELL Span12Mux_v8 +IOPATH I O 333.689:433.5:527.183 366.404:476:578.868 + +CELL Span12Mux_v9 +IOPATH I O 353.318:459:558.194 392.576:510:620.215 + +CELL Span12Mux_v10 +IOPATH I O 366.404:476:578.868 405.662:527:640.889 + +CELL Span12Mux_v11 +IOPATH I O 386.033:501.5:609.878 425.29:552.5:671.9 + +CELL Span12Mux_v12 +IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 + +CELL SRMux +IOPATH I O 431.833:561:682.237 333.689:433.5:527.183 + diff --git a/icefuzz/timings_8k.txt b/icefuzz/timings_8k.txt new file mode 100644 index 0000000..4a60b63 --- /dev/null +++ b/icefuzz/timings_8k.txt @@ -0,0 +1,528 @@ +CELL CascadeMux +IOPATH I O 0:0:0 0:0:0 + +CELL CEMux +IOPATH I O 562.692:731:888.975 516.892:671.5:816.617 + +CELL ClkMux +IOPATH I O 287.889:374:454.825 215.917:280.5:341.118 + +CELL gio2CtrlBuf +IOPATH I O 0:0:0 0:0:0 + +CELL Glb2LocalMux +IOPATH I O 418.748:544:661.563 333.689:433.5:527.183 + +CELL GlobalMux +IOPATH I O 143.944:187:227.412 71.9722:93.5:113.706 + +CELL ICE_CARRY_IN_MUX +IOPATH carryinitin carryinitout 183.202:238:289.434 163.573:212.5:258.423 + +CELL ICE_GB +IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 575.778:748:909.649 523.434:680:826.954 + +CELL InMux +IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445 + +CELL INV +IOPATH I O 0:0:0 0:0:0 + +CELL IO_PAD +IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 +IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990 +IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942 +IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 +IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540 + +CELL IoInMux +IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445 + +CELL IoSpan4Mux +IOPATH I O 268.26:348.5:423.814 300.975:391:475.498 + +CELL LocalMux +IOPATH I O 307.518:399.5:485.835 287.889:374:454.825 + +CELL LogicCell40 +HOLD negedge:ce posedge:clk 0:0:0 +HOLD negedge:in0 posedge:clk 0:0:0 +HOLD negedge:in1 posedge:clk 0:0:0 +HOLD negedge:in2 posedge:clk 0:0:0 +HOLD negedge:in3 posedge:clk 0:0:0 +HOLD negedge:sr posedge:clk -184.184:-239.275:-290.984 +HOLD posedge:ce posedge:clk 0:0:0 +HOLD posedge:in0 posedge:clk 0:0:0 +HOLD posedge:in1 posedge:clk 0:0:0 +HOLD posedge:in2 posedge:clk 0:0:0 +HOLD posedge:in3 posedge:clk 0:0:0 +HOLD posedge:sr posedge:clk -167.106:-217.09:-264.005 +RECOVERY negedge:sr posedge:clk 148.983:193.545:235.372 +RECOVERY posedge:sr posedge:clk 0:0:0 +REMOVAL negedge:sr posedge:clk 0:0:0 +REMOVAL posedge:sr posedge:clk 0:0:0 +SETUP negedge:ce posedge:clk 0:0:0 +SETUP negedge:in0 posedge:clk 372.947:484.5:589.205 +SETUP negedge:in1 posedge:clk 353.318:459:558.194 +SETUP negedge:in2 posedge:clk 300.975:391:475.498 +SETUP negedge:in3 posedge:clk 202.831:263.5:320.445 +SETUP negedge:sr posedge:clk 130.859:170:206.738 +SETUP posedge:ce posedge:clk 0:0:0 +SETUP posedge:in0 posedge:clk 438.376:569.5:692.574 +SETUP posedge:in1 posedge:clk 372.947:484.5:589.205 +SETUP posedge:in2 posedge:clk 346.775:450.5:547.857 +SETUP posedge:in3 posedge:clk 255.174:331.5:403.14 +SETUP posedge:sr posedge:clk 189.745:246.5:299.771 +IOPATH carryin carryout 117.773:153:186.065 98.144:127.5:155.054 +IOPATH in0 lcout 418.748:544:661.563 359.861:467.5:568.531 +IOPATH in0 ltout 340.232:442:537.52 359.861:467.5:568.531 +IOPATH in1 carryout 242.088:314.5:382.466 229.003:297.5:361.792 +IOPATH in1 lcout 372.947:484.5:589.205 353.318:459:558.194 +IOPATH in1 ltout 300.975:391:475.498 353.318:459:558.194 +IOPATH in2 carryout 215.917:280.5:341.118 124.316:161.5:196.402 +IOPATH in2 lcout 353.318:459:558.194 327.147:425:516.846 +IOPATH in2 ltout 287.889:374:454.825 320.604:416.5:506.509 +IOPATH in3 lcout 294.432:382.5:465.161 268.26:348.5:423.814 +IOPATH in3 ltout 248.631:323:392.803 255.174:331.5:403.14 +IOPATH posedge:clk lcout 503.806:654.5:795.943 503.806:654.5:795.943 +IOPATH sr lcout 0:0:0 558.989:726.189:883.125 +IOPATH sr lcout 558.963:726.155:883.083 0:0:0 + +CELL Odrv4 +IOPATH I O 327.147:425:516.846 346.775:450.5:547.857 + +CELL Odrv12 +IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 + +CELL PLL40 +IOPATH PLLIN PLLOUTCORE *:*:* *:*:* +IOPATH PLLIN PLLOUTGLOBAL *:*:* *:*:* + +CELL PLL40_2 +IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* +IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* +IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* +IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* + +CELL PLL40_2F +IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* +IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* +IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* +IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* + +CELL PRE_IO +HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 +HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 +HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0 +HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0 +HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 +HOLD negedge:PADIN negedge:INPUTCLK 0:0:0 +HOLD negedge:PADIN posedge:INPUTCLK 0:0:0 +HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 +HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 +HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0 +HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0 +HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 +HOLD posedge:PADIN negedge:INPUTCLK 0:0:0 +HOLD posedge:PADIN posedge:INPUTCLK 0:0:0 +SETUP negedge:CLOCKENABLE posedge:INPUTCLK 65.4293:85:103.369 +SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 65.4293:85:103.369 +SETUP negedge:DOUT0 posedge:OUTPUTCLK 65.4293:85:103.369 +SETUP negedge:DOUT1 negedge:OUTPUTCLK 65.4293:85:103.369 +SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 65.4293:85:103.369 +SETUP negedge:PADIN negedge:INPUTCLK 1758.87:2284.97:2778.77 +SETUP negedge:PADIN posedge:INPUTCLK 1758.87:2284.97:2778.77 +SETUP posedge:CLOCKENABLE posedge:INPUTCLK 71.9722:93.5:113.706 +SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706 +SETUP posedge:DOUT0 posedge:OUTPUTCLK 71.9722:93.5:113.706 +SETUP posedge:DOUT1 negedge:OUTPUTCLK 71.9722:93.5:113.706 +SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706 +SETUP posedge:PADIN negedge:INPUTCLK 1765.41:2293.47:2789.11 +SETUP posedge:PADIN posedge:INPUTCLK 1765.41:2293.47:2789.11 +IOPATH DOUT0 PADOUT 1871.28:2431:2956.36 2087.19:2711.5:3297.48 +IOPATH LATCHINPUTVALUE DIN0 320.604:416.5:506.509 346.775:450.5:547.857 +IOPATH negedge:INPUTCLK DIN1 130.859:170:206.738 130.859:170:206.738 +IOPATH negedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738 +IOPATH OUTPUTENABLE PADOEN 163.573:212.5:258.423 196.288:255:310.108 +IOPATH PADIN DIN0 575.778:748:909.649 431.833:561:682.237 +IOPATH posedge:INPUTCLK DIN0 130.859:170:206.738 130.859:170:206.738 +IOPATH posedge:OUTPUTCLK PADOEN 104.687:136:165.391 130.859:170:206.738 +IOPATH posedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738 + +CELL PRE_IO_GBUF +IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1737.34:2257:2744.76 1593.4:2070:2517.35 + +CELL SB_PLL40_2F_CORE +IOPATH REFERENCECLK PLLOUTCOREA *:*:* *:*:* +IOPATH REFERENCECLK PLLOUTCOREB *:*:* *:*:* +IOPATH REFERENCECLK PLLOUTGLOBALA *:*:* *:*:* +IOPATH REFERENCECLK PLLOUTGLOBALB *:*:* *:*:* + +CELL SB_PLL40_CORE +IOPATH REFERENCECLK PLLOUTCORE *:*:* *:*:* +IOPATH REFERENCECLK PLLOUTGLOBAL *:*:* *:*:* + +CELL SB_RAM40_4K +HOLD negedge:MASK[0] posedge:WCLK 0:0:0 +HOLD negedge:MASK[1] posedge:WCLK 0:0:0 +HOLD negedge:MASK[2] posedge:WCLK 0:0:0 +HOLD negedge:MASK[3] posedge:WCLK 0:0:0 +HOLD negedge:MASK[4] posedge:WCLK 0:0:0 +HOLD negedge:MASK[5] posedge:WCLK 0:0:0 +HOLD negedge:MASK[6] posedge:WCLK 0:0:0 +HOLD negedge:MASK[7] posedge:WCLK 0:0:0 +HOLD negedge:MASK[8] posedge:WCLK 0:0:0 +HOLD negedge:MASK[9] posedge:WCLK 0:0:0 +HOLD negedge:MASK[10] posedge:WCLK 0:0:0 +HOLD negedge:MASK[11] posedge:WCLK 0:0:0 +HOLD negedge:MASK[12] posedge:WCLK 0:0:0 +HOLD negedge:MASK[13] posedge:WCLK 0:0:0 +HOLD negedge:MASK[14] posedge:WCLK 0:0:0 +HOLD negedge:MASK[15] posedge:WCLK 0:0:0 +HOLD negedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954 +HOLD negedge:RCLKE posedge:RCLK 49.072:63.75:77.5269 +HOLD negedge:RE posedge:RCLK 78.5152:102:124.043 +HOLD negedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WCLKE posedge:WCLK 25.5174:33.15:40.314 +HOLD negedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846 +HOLD negedge:WE posedge:WCLK 45.8005:59.5:72.3585 +HOLD posedge:MASK[0] posedge:WCLK 0:0:0 +HOLD posedge:MASK[1] posedge:WCLK 0:0:0 +HOLD posedge:MASK[2] posedge:WCLK 0:0:0 +HOLD posedge:MASK[3] posedge:WCLK 0:0:0 +HOLD posedge:MASK[4] posedge:WCLK 0:0:0 +HOLD posedge:MASK[5] posedge:WCLK 0:0:0 +HOLD posedge:MASK[6] posedge:WCLK 0:0:0 +HOLD posedge:MASK[7] posedge:WCLK 0:0:0 +HOLD posedge:MASK[8] posedge:WCLK 0:0:0 +HOLD posedge:MASK[9] posedge:WCLK 0:0:0 +HOLD posedge:MASK[10] posedge:WCLK 0:0:0 +HOLD posedge:MASK[11] posedge:WCLK 0:0:0 +HOLD posedge:MASK[12] posedge:WCLK 0:0:0 +HOLD posedge:MASK[13] posedge:WCLK 0:0:0 +HOLD posedge:MASK[14] posedge:WCLK 0:0:0 +HOLD posedge:MASK[15] posedge:WCLK 0:0:0 +HOLD posedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954 +HOLD posedge:RCLKE posedge:RCLK 49.072:63.75:77.5269 +HOLD posedge:RE posedge:RCLK 78.5152:102:124.043 +HOLD posedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WCLKE posedge:WCLK 25.5174:33.15:40.314 +HOLD posedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846 +HOLD posedge:WE posedge:WCLK 45.8005:59.5:72.3585 +SETUP negedge:MASK[0] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[1] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[2] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[3] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[4] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[5] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[6] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[7] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[8] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[9] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[10] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[11] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[12] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[13] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[14] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:MASK[15] posedge:WCLK 255.174:331.5:403.14 +SETUP negedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771 +SETUP negedge:RCLKE posedge:RCLK 248.631:323:392.803 +SETUP negedge:RE posedge:RCLK 91.601:119:144.717 +SETUP negedge:WADDR[0] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[1] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[2] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[3] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[4] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[5] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[6] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[7] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[8] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[9] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WADDR[10] posedge:WCLK 209.374:272:330.781 +SETUP negedge:WCLKE posedge:WCLK 248.631:323:392.803 +SETUP negedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749 +SETUP negedge:WE posedge:WCLK 124.316:161.5:196.402 +SETUP posedge:MASK[0] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[1] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[2] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[3] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[4] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[5] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[6] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[7] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[8] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[9] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[10] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[11] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[12] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[13] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[14] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:MASK[15] posedge:WCLK 255.174:331.5:403.14 +SETUP posedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771 +SETUP posedge:RCLKE posedge:RCLK 248.631:323:392.803 +SETUP posedge:RE posedge:RCLK 91.601:119:144.717 +SETUP posedge:WADDR[0] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[1] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[2] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[3] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[4] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[5] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[6] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[7] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[8] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[9] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WADDR[10] posedge:WCLK 209.374:272:330.781 +SETUP posedge:WCLKE posedge:WCLK 248.631:323:392.803 +SETUP posedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749 +SETUP posedge:WE posedge:WCLK 124.316:161.5:196.402 +IOPATH posedge:RCLK RDATA[0] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[1] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[2] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[3] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[4] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[5] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[6] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[7] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[8] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[9] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[10] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[11] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[12] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[13] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[14] 2002.14:2601:3163.1 2002.14:2601:3163.1 +IOPATH posedge:RCLK RDATA[15] 2002.14:2601:3163.1 2002.14:2601:3163.1 + +CELL Sp12to4 +IOPATH I O 399.119:518.5:630.552 418.748:544:661.563 + +CELL Span4Mux_h0 +IOPATH I O 137.402:178.5:217.075 130.859:170:206.738 + +CELL Span4Mux_h1 +IOPATH I O 163.573:212.5:258.423 157.03:204:248.086 + +CELL Span4Mux_h2 +IOPATH I O 189.745:246.5:299.771 189.745:246.5:299.771 + +CELL Span4Mux_h3 +IOPATH I O 215.917:280.5:341.118 215.917:280.5:341.118 + +CELL Span4Mux_h4 +IOPATH I O 281.346:365.5:444.488 294.432:382.5:465.161 + +CELL Span4Mux_v0 +IOPATH I O 189.745:246.5:299.771 176.659:229.5:279.097 + +CELL Span4Mux_v1 +IOPATH I O 189.745:246.5:299.771 183.202:238:289.434 + +CELL Span4Mux_v2 +IOPATH I O 235.546:306:372.129 235.546:306:372.129 + +CELL Span4Mux_v3 +IOPATH I O 294.432:382.5:465.161 314.061:408:496.172 + +CELL Span4Mux_v4 +IOPATH I O 327.147:425:516.846 346.775:450.5:547.857 + +CELL Span12Mux_h0 +IOPATH I O 130.859:170:206.738 137.402:178.5:217.075 + +CELL Span12Mux_h1 +IOPATH I O 124.316:161.5:196.402 124.316:161.5:196.402 + +CELL Span12Mux_h2 +IOPATH I O 150.487:195.5:237.749 157.03:204:248.086 + +CELL Span12Mux_h3 +IOPATH I O 157.03:204:248.086 170.116:221:268.76 + +CELL Span12Mux_h4 +IOPATH I O 183.202:238:289.434 202.831:263.5:320.445 + +CELL Span12Mux_h5 +IOPATH I O 215.917:280.5:341.118 242.088:314.5:382.466 + +CELL Span12Mux_h6 +IOPATH I O 235.546:306:372.129 261.717:340:413.477 + +CELL Span12Mux_h7 +IOPATH I O 268.26:348.5:423.814 300.975:391:475.498 + +CELL Span12Mux_h8 +IOPATH I O 320.604:416.5:506.509 359.861:467.5:568.531 + +CELL Span12Mux_h9 +IOPATH I O 366.404:476:578.868 405.662:527:640.889 + +CELL Span12Mux_h10 +IOPATH I O 399.119:518.5:630.552 438.376:569.5:692.574 + +CELL Span12Mux_h11 +IOPATH I O 438.376:569.5:692.574 490.72:637.5:775.269 + +CELL Span12Mux_h12 +IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 + +CELL Span12Mux_v0 +IOPATH I O 91.601:119:144.717 98.144:127.5:155.054 + +CELL Span12Mux_v1 +IOPATH I O 98.144:127.5:155.054 98.144:127.5:155.054 + +CELL Span12Mux_v2 +IOPATH I O 130.859:170:206.738 143.944:187:227.412 + +CELL Span12Mux_v3 +IOPATH I O 137.402:178.5:217.075 157.03:204:248.086 + +CELL Span12Mux_v4 +IOPATH I O 170.116:221:268.76 196.288:255:310.108 + +CELL Span12Mux_v5 +IOPATH I O 222.46:289:351.455 248.631:323:392.803 + +CELL Span12Mux_v6 +IOPATH I O 242.088:314.5:382.466 268.26:348.5:423.814 + +CELL Span12Mux_v7 +IOPATH I O 261.717:340:413.477 294.432:382.5:465.161 + +CELL Span12Mux_v8 +IOPATH I O 333.689:433.5:527.183 366.404:476:578.868 + +CELL Span12Mux_v9 +IOPATH I O 353.318:459:558.194 392.576:510:620.215 + +CELL Span12Mux_v10 +IOPATH I O 366.404:476:578.868 405.662:527:640.889 + +CELL Span12Mux_v11 +IOPATH I O 386.033:501.5:609.878 425.29:552.5:671.9 + +CELL Span12Mux_v12 +IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 + +CELL SRMux +IOPATH I O 431.833:561:682.237 333.689:433.5:527.183 + diff --git a/icefuzz/tmedges.ys b/icefuzz/tmedges.ys new file mode 100644 index 0000000..ab25f2d --- /dev/null +++ b/icefuzz/tmedges.ys @@ -0,0 +1,20 @@ +hierarchy -generate LogicCell40 i:in* i:*in i:clk i:ce i:sr o:*out +hierarchy -generate ICE_GB i:USERSIGNALTOGLOBALBUFFER o:GLOBALBUFFEROUTPUT +hierarchy -generate PRE_IO_GBUF i:PADSIGNALTOGLOBALBUFFER o:GLOBALBUFFEROUTPUT +hierarchy -generate VCC o:* +hierarchy -generate GND o:* +hierarchy -generate IO_PAD i:OE i:DIN o:DOUT io:PACKAGEPIN +hierarchy -generate PRE_IO o:PADOEN o:PADOUT i:PADIN i:CLOCKENABLE o:DIN0 o:DIN1 \ + i:DOUT0 i:DOUT1 i:INPUTCLK i:LATCHINPUTVALUE i:OUTPUTCLK i:OUTPUTENABLE +hierarchy -generate *PLL40* i:PACKAGEPIN i:BYPASS i:DYNAMICDELAY i:EXTFEEDBACK i:LATCHINPUTVALUE \ + o:LOCK o:PLLOUT* i:REFERENCECLK i:RESETB i:SCLK i:SDI o:SDO i:PLLIN +hierarchy -generate SB_RAM40_4K o:RDATA i:RADDR i:WADDR i:MASK i:WDATA i:RCLKE i:RCLK i:RE i:WCLKE i:WCLK i:WE +hierarchy -generate ICE_CARRY_IN_MUX i:*in o:*out +hierarchy -generate *Mux* i:I o:O +hierarchy -generate Odrv* i:I o:O +hierarchy -generate Sp12to4 i:I o:O +hierarchy -generate INV i:I o:O +hierarchy -generate gio2CtrlBuf i:I o:O + +hierarchy -check +tee -a tmedges.tmp edgetypes diff --git a/icefuzz/tmedges_1k.txt b/icefuzz/tmedges_1k.txt new file mode 100644 index 0000000..2794758 --- /dev/null +++ b/icefuzz/tmedges_1k.txt @@ -0,0 +1,612 @@ +CEMux.O LogicCell40.ce +CEMux.O PRE_IO.CLOCKENABLE +CEMux.O SB_RAM40_4K.RCLKE +CEMux.O SB_RAM40_4K.WCLKE +CascadeMux.O LogicCell40.in2 +CascadeMux.O SB_RAM40_4K.RADDR[0] +CascadeMux.O SB_RAM40_4K.RADDR[10] +CascadeMux.O SB_RAM40_4K.RADDR[1] +CascadeMux.O SB_RAM40_4K.RADDR[2] +CascadeMux.O SB_RAM40_4K.RADDR[3] +CascadeMux.O SB_RAM40_4K.RADDR[4] +CascadeMux.O SB_RAM40_4K.RADDR[5] +CascadeMux.O SB_RAM40_4K.RADDR[6] +CascadeMux.O SB_RAM40_4K.RADDR[7] +CascadeMux.O SB_RAM40_4K.RADDR[8] +CascadeMux.O SB_RAM40_4K.RADDR[9] +CascadeMux.O SB_RAM40_4K.WADDR[0] +CascadeMux.O SB_RAM40_4K.WADDR[10] +CascadeMux.O SB_RAM40_4K.WADDR[1] +CascadeMux.O SB_RAM40_4K.WADDR[2] +CascadeMux.O SB_RAM40_4K.WADDR[3] +CascadeMux.O SB_RAM40_4K.WADDR[4] +CascadeMux.O SB_RAM40_4K.WADDR[5] +CascadeMux.O SB_RAM40_4K.WADDR[6] +CascadeMux.O SB_RAM40_4K.WADDR[7] +CascadeMux.O SB_RAM40_4K.WADDR[8] +CascadeMux.O SB_RAM40_4K.WADDR[9] +ClkMux.O INV.I +ClkMux.O LogicCell40.clk +ClkMux.O PRE_IO.INPUTCLK +ClkMux.O PRE_IO.OUTPUTCLK +ClkMux.O SB_RAM40_4K.RCLK +ClkMux.O SB_RAM40_4K.WCLK +GND.Y LogicCell40.carryin +GND.Y LogicCell40.clk +GND.Y LogicCell40.in0 +GND.Y LogicCell40.in1 +GND.Y LogicCell40.in2 +GND.Y LogicCell40.in3 +GND.Y LogicCell40.sr +GND.Y PRE_IO.DOUT0 +Glb2LocalMux.O LocalMux.I +GlobalMux.O CEMux.I +GlobalMux.O ClkMux.I +GlobalMux.O Glb2LocalMux.I +GlobalMux.O SRMux.I +ICE_CARRY_IN_MUX.carryinitout InMux.I +ICE_CARRY_IN_MUX.carryinitout LogicCell40.carryin +ICE_GB.GLOBALBUFFEROUTPUT gio2CtrlBuf.I +INV.O LogicCell40.clk +INV.O SB_RAM40_4K.RCLK +INV.O SB_RAM40_4K.WCLK +IO_PAD.DOUT PLL40.PLLIN +IO_PAD.DOUT PLL40_2.PLLIN +IO_PAD.DOUT PLL40_2F.PLLIN +IO_PAD.DOUT PRE_IO.PADIN +IO_PAD.DOUT PRE_IO_GBUF.PADSIGNALTOGLOBALBUFFER +IO_PAD.PACKAGEPIN IO_PAD.PACKAGEPIN +InMux.O CascadeMux.I +InMux.O LogicCell40.in0 +InMux.O LogicCell40.in1 +InMux.O LogicCell40.in3 +InMux.O SB_RAM40_4K.MASK[0] +InMux.O SB_RAM40_4K.MASK[10] +InMux.O SB_RAM40_4K.MASK[11] +InMux.O SB_RAM40_4K.MASK[12] +InMux.O SB_RAM40_4K.MASK[13] +InMux.O SB_RAM40_4K.MASK[14] +InMux.O SB_RAM40_4K.MASK[15] +InMux.O SB_RAM40_4K.MASK[1] +InMux.O SB_RAM40_4K.MASK[2] +InMux.O SB_RAM40_4K.MASK[3] +InMux.O SB_RAM40_4K.MASK[4] +InMux.O SB_RAM40_4K.MASK[5] +InMux.O SB_RAM40_4K.MASK[6] +InMux.O SB_RAM40_4K.MASK[7] +InMux.O SB_RAM40_4K.MASK[8] +InMux.O SB_RAM40_4K.MASK[9] +InMux.O SB_RAM40_4K.WDATA[0] +InMux.O SB_RAM40_4K.WDATA[10] +InMux.O SB_RAM40_4K.WDATA[11] +InMux.O SB_RAM40_4K.WDATA[12] +InMux.O SB_RAM40_4K.WDATA[13] +InMux.O SB_RAM40_4K.WDATA[14] +InMux.O SB_RAM40_4K.WDATA[15] +InMux.O SB_RAM40_4K.WDATA[1] +InMux.O SB_RAM40_4K.WDATA[2] +InMux.O SB_RAM40_4K.WDATA[3] +InMux.O SB_RAM40_4K.WDATA[4] +InMux.O SB_RAM40_4K.WDATA[5] +InMux.O SB_RAM40_4K.WDATA[6] +InMux.O SB_RAM40_4K.WDATA[7] +InMux.O SB_RAM40_4K.WDATA[8] +InMux.O SB_RAM40_4K.WDATA[9] +IoInMux.O ICE_GB.USERSIGNALTOGLOBALBUFFER +IoInMux.O PLL40.BYPASS +IoInMux.O PLL40.DYNAMICDELAY[0] +IoInMux.O PLL40.DYNAMICDELAY[1] +IoInMux.O PLL40.DYNAMICDELAY[2] +IoInMux.O PLL40.DYNAMICDELAY[3] +IoInMux.O PLL40.DYNAMICDELAY[4] +IoInMux.O PLL40.DYNAMICDELAY[5] +IoInMux.O PLL40.DYNAMICDELAY[6] +IoInMux.O PLL40.DYNAMICDELAY[7] +IoInMux.O PLL40.EXTFEEDBACK +IoInMux.O PLL40.LATCHINPUTVALUE +IoInMux.O PLL40.RESETB +IoInMux.O PLL40.SCLK +IoInMux.O PLL40.SDI +IoInMux.O PLL40_2.BYPASS +IoInMux.O PLL40_2.DYNAMICDELAY[0] +IoInMux.O PLL40_2.DYNAMICDELAY[1] +IoInMux.O PLL40_2.DYNAMICDELAY[2] +IoInMux.O PLL40_2.DYNAMICDELAY[3] +IoInMux.O PLL40_2.DYNAMICDELAY[4] +IoInMux.O PLL40_2.DYNAMICDELAY[5] +IoInMux.O PLL40_2.DYNAMICDELAY[6] +IoInMux.O PLL40_2.DYNAMICDELAY[7] +IoInMux.O PLL40_2.EXTFEEDBACK +IoInMux.O PLL40_2.LATCHINPUTVALUE +IoInMux.O PLL40_2.RESETB +IoInMux.O PLL40_2.SCLK +IoInMux.O PLL40_2.SDI +IoInMux.O PLL40_2F.BYPASS +IoInMux.O PLL40_2F.DYNAMICDELAY[0] +IoInMux.O PLL40_2F.DYNAMICDELAY[1] +IoInMux.O PLL40_2F.DYNAMICDELAY[2] +IoInMux.O PLL40_2F.DYNAMICDELAY[3] +IoInMux.O PLL40_2F.DYNAMICDELAY[4] +IoInMux.O PLL40_2F.DYNAMICDELAY[5] +IoInMux.O PLL40_2F.DYNAMICDELAY[6] +IoInMux.O PLL40_2F.DYNAMICDELAY[7] +IoInMux.O PLL40_2F.EXTFEEDBACK +IoInMux.O PLL40_2F.LATCHINPUTVALUE +IoInMux.O PLL40_2F.RESETB +IoInMux.O PLL40_2F.SCLK +IoInMux.O PLL40_2F.SDI +IoInMux.O PRE_IO.DOUT0 +IoInMux.O PRE_IO.DOUT1 +IoInMux.O PRE_IO.LATCHINPUTVALUE +IoInMux.O PRE_IO.OUTPUTENABLE +IoInMux.O SB_PLL40_2F_CORE.BYPASS +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[0] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[1] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[2] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[3] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[4] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[5] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[6] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[7] +IoInMux.O SB_PLL40_2F_CORE.EXTFEEDBACK +IoInMux.O SB_PLL40_2F_CORE.LATCHINPUTVALUE +IoInMux.O SB_PLL40_2F_CORE.REFERENCECLK +IoInMux.O SB_PLL40_2F_CORE.RESETB +IoInMux.O SB_PLL40_2F_CORE.SCLK +IoInMux.O SB_PLL40_2F_CORE.SDI +IoInMux.O SB_PLL40_CORE.BYPASS +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[0] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[1] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[2] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[3] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[4] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[5] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[6] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[7] +IoInMux.O SB_PLL40_CORE.EXTFEEDBACK +IoInMux.O SB_PLL40_CORE.LATCHINPUTVALUE +IoInMux.O SB_PLL40_CORE.REFERENCECLK +IoInMux.O SB_PLL40_CORE.RESETB +IoInMux.O SB_PLL40_CORE.SCLK +IoInMux.O SB_PLL40_CORE.SDI +IoSpan4Mux.O IoSpan4Mux.I +IoSpan4Mux.O LocalMux.I +IoSpan4Mux.O Span4Mux_h.I +IoSpan4Mux.O Span4Mux_s0_h.I +IoSpan4Mux.O Span4Mux_s0_v.I +IoSpan4Mux.O Span4Mux_s1_h.I +IoSpan4Mux.O Span4Mux_s1_v.I +IoSpan4Mux.O Span4Mux_s2_h.I +IoSpan4Mux.O Span4Mux_s2_v.I +IoSpan4Mux.O Span4Mux_s3_h.I +IoSpan4Mux.O Span4Mux_s3_v.I +IoSpan4Mux.O Span4Mux_v.I +LocalMux.O CEMux.I +LocalMux.O ClkMux.I +LocalMux.O InMux.I +LocalMux.O IoInMux.I +LocalMux.O SRMux.I +LogicCell40.carryout ICE_CARRY_IN_MUX.carryinitin +LogicCell40.carryout InMux.I +LogicCell40.carryout LogicCell40.carryin +LogicCell40.lcout LocalMux.I +LogicCell40.lcout Odrv12.I +LogicCell40.lcout Odrv4.I +LogicCell40.ltout CascadeMux.I +Odrv12.O LocalMux.I +Odrv12.O Sp12to4.I +Odrv12.O Span12Mux_s0_h.I +Odrv12.O Span12Mux_s0_v.I +Odrv12.O Span12Mux_s10_h.I +Odrv12.O Span12Mux_s10_v.I +Odrv12.O Span12Mux_s11_h.I +Odrv12.O Span12Mux_s11_v.I +Odrv12.O Span12Mux_s1_h.I +Odrv12.O Span12Mux_s1_v.I +Odrv12.O Span12Mux_s2_h.I +Odrv12.O Span12Mux_s2_v.I +Odrv12.O Span12Mux_s3_h.I +Odrv12.O Span12Mux_s3_v.I +Odrv12.O Span12Mux_s4_h.I +Odrv12.O Span12Mux_s4_v.I +Odrv12.O Span12Mux_s5_h.I +Odrv12.O Span12Mux_s5_v.I +Odrv12.O Span12Mux_s6_h.I +Odrv12.O Span12Mux_s6_v.I +Odrv12.O Span12Mux_s7_h.I +Odrv12.O Span12Mux_s7_v.I +Odrv12.O Span12Mux_s8_h.I +Odrv12.O Span12Mux_s8_v.I +Odrv12.O Span12Mux_s9_h.I +Odrv12.O Span12Mux_s9_v.I +Odrv12.O Span12Mux_v.I +Odrv4.O IoSpan4Mux.I +Odrv4.O LocalMux.I +Odrv4.O Span4Mux_h.I +Odrv4.O Span4Mux_s0_h.I +Odrv4.O Span4Mux_s0_v.I +Odrv4.O Span4Mux_s1_h.I +Odrv4.O Span4Mux_s1_v.I +Odrv4.O Span4Mux_s2_h.I +Odrv4.O Span4Mux_s2_v.I +Odrv4.O Span4Mux_s3_h.I +Odrv4.O Span4Mux_s3_v.I +Odrv4.O Span4Mux_v.I +PLL40.LOCK LocalMux.I +PLL40.PLLOUTCORE LocalMux.I +PLL40.PLLOUTCORE Odrv12.I +PLL40.PLLOUTCORE Odrv4.I +PLL40.PLLOUTGLOBAL GlobalMux.I +PLL40.SDO LocalMux.I +PLL40_2.LOCK LocalMux.I +PLL40_2.PLLOUTCOREA LocalMux.I +PLL40_2.PLLOUTCOREA Odrv12.I +PLL40_2.PLLOUTCOREA Odrv4.I +PLL40_2.PLLOUTCOREB LocalMux.I +PLL40_2.PLLOUTCOREB Odrv12.I +PLL40_2.PLLOUTCOREB Odrv4.I +PLL40_2.PLLOUTGLOBALA GlobalMux.I +PLL40_2.PLLOUTGLOBALB GlobalMux.I +PLL40_2.SDO LocalMux.I +PLL40_2F.LOCK LocalMux.I +PLL40_2F.PLLOUTCOREA LocalMux.I +PLL40_2F.PLLOUTCOREA Odrv12.I +PLL40_2F.PLLOUTCOREA Odrv4.I +PLL40_2F.PLLOUTCOREB LocalMux.I +PLL40_2F.PLLOUTCOREB Odrv12.I +PLL40_2F.PLLOUTCOREB Odrv4.I +PLL40_2F.PLLOUTGLOBALA GlobalMux.I +PLL40_2F.PLLOUTGLOBALB GlobalMux.I +PLL40_2F.SDO LocalMux.I +PRE_IO.DIN0 LocalMux.I +PRE_IO.DIN0 Odrv12.I +PRE_IO.DIN0 Odrv4.I +PRE_IO.DIN1 LocalMux.I +PRE_IO.DIN1 Odrv12.I +PRE_IO.DIN1 Odrv4.I +PRE_IO.PADOEN IO_PAD.OE +PRE_IO.PADOUT IO_PAD.DIN +PRE_IO_GBUF.GLOBALBUFFEROUTPUT gio2CtrlBuf.I +SB_PLL40_2F_CORE.LOCK LocalMux.I +SB_PLL40_2F_CORE.PLLOUTCOREA LocalMux.I +SB_PLL40_2F_CORE.PLLOUTCOREA Odrv12.I +SB_PLL40_2F_CORE.PLLOUTCOREA Odrv4.I +SB_PLL40_2F_CORE.PLLOUTCOREB LocalMux.I +SB_PLL40_2F_CORE.PLLOUTCOREB Odrv12.I +SB_PLL40_2F_CORE.PLLOUTCOREB Odrv4.I +SB_PLL40_2F_CORE.PLLOUTGLOBALA GlobalMux.I +SB_PLL40_2F_CORE.PLLOUTGLOBALB GlobalMux.I +SB_PLL40_2F_CORE.SDO LocalMux.I +SB_PLL40_CORE.LOCK LocalMux.I +SB_PLL40_CORE.PLLOUTCORE LocalMux.I +SB_PLL40_CORE.PLLOUTCORE Odrv12.I +SB_PLL40_CORE.PLLOUTCORE Odrv4.I +SB_PLL40_CORE.PLLOUTGLOBAL GlobalMux.I +SB_PLL40_CORE.SDO LocalMux.I +SB_RAM40_4K.RDATA[0] LocalMux.I +SB_RAM40_4K.RDATA[0] Odrv12.I +SB_RAM40_4K.RDATA[0] Odrv4.I +SB_RAM40_4K.RDATA[10] LocalMux.I +SB_RAM40_4K.RDATA[10] Odrv12.I +SB_RAM40_4K.RDATA[10] Odrv4.I +SB_RAM40_4K.RDATA[11] LocalMux.I +SB_RAM40_4K.RDATA[11] Odrv12.I +SB_RAM40_4K.RDATA[11] Odrv4.I +SB_RAM40_4K.RDATA[12] LocalMux.I +SB_RAM40_4K.RDATA[12] Odrv12.I +SB_RAM40_4K.RDATA[12] Odrv4.I +SB_RAM40_4K.RDATA[13] LocalMux.I +SB_RAM40_4K.RDATA[13] Odrv12.I +SB_RAM40_4K.RDATA[13] Odrv4.I +SB_RAM40_4K.RDATA[14] LocalMux.I +SB_RAM40_4K.RDATA[14] Odrv12.I +SB_RAM40_4K.RDATA[14] Odrv4.I +SB_RAM40_4K.RDATA[15] LocalMux.I +SB_RAM40_4K.RDATA[15] Odrv12.I +SB_RAM40_4K.RDATA[15] Odrv4.I +SB_RAM40_4K.RDATA[1] LocalMux.I +SB_RAM40_4K.RDATA[1] Odrv12.I +SB_RAM40_4K.RDATA[1] Odrv4.I +SB_RAM40_4K.RDATA[2] LocalMux.I +SB_RAM40_4K.RDATA[2] Odrv12.I +SB_RAM40_4K.RDATA[2] Odrv4.I +SB_RAM40_4K.RDATA[3] LocalMux.I +SB_RAM40_4K.RDATA[3] Odrv12.I +SB_RAM40_4K.RDATA[3] Odrv4.I +SB_RAM40_4K.RDATA[4] LocalMux.I +SB_RAM40_4K.RDATA[4] Odrv12.I +SB_RAM40_4K.RDATA[4] Odrv4.I +SB_RAM40_4K.RDATA[5] LocalMux.I +SB_RAM40_4K.RDATA[5] Odrv12.I +SB_RAM40_4K.RDATA[5] Odrv4.I +SB_RAM40_4K.RDATA[6] LocalMux.I +SB_RAM40_4K.RDATA[6] Odrv12.I +SB_RAM40_4K.RDATA[6] Odrv4.I +SB_RAM40_4K.RDATA[7] LocalMux.I +SB_RAM40_4K.RDATA[7] Odrv12.I +SB_RAM40_4K.RDATA[7] Odrv4.I +SB_RAM40_4K.RDATA[8] LocalMux.I +SB_RAM40_4K.RDATA[8] Odrv12.I +SB_RAM40_4K.RDATA[8] Odrv4.I +SB_RAM40_4K.RDATA[9] LocalMux.I +SB_RAM40_4K.RDATA[9] Odrv12.I +SB_RAM40_4K.RDATA[9] Odrv4.I +SRMux.O LogicCell40.sr +SRMux.O SB_RAM40_4K.RE +SRMux.O SB_RAM40_4K.WE +Sp12to4.O IoSpan4Mux.I +Sp12to4.O LocalMux.I +Sp12to4.O Span4Mux_h.I +Sp12to4.O Span4Mux_s0_h.I +Sp12to4.O Span4Mux_s0_v.I +Sp12to4.O Span4Mux_s1_h.I +Sp12to4.O Span4Mux_s1_v.I +Sp12to4.O Span4Mux_s2_h.I +Sp12to4.O Span4Mux_s2_v.I +Sp12to4.O Span4Mux_s3_h.I +Sp12to4.O Span4Mux_s3_v.I +Sp12to4.O Span4Mux_v.I +Span12Mux_s0_h.O LocalMux.I +Span12Mux_s0_h.O Sp12to4.I +Span12Mux_s0_h.O Span12Mux_s11_h.I +Span12Mux_s0_h.O Span12Mux_s1_v.I +Span12Mux_s0_v.O LocalMux.I +Span12Mux_s0_v.O Sp12to4.I +Span12Mux_s0_v.O Span12Mux_v.I +Span12Mux_s10_h.O LocalMux.I +Span12Mux_s10_h.O Sp12to4.I +Span12Mux_s10_h.O Span12Mux_s2_v.I +Span12Mux_s10_h.O Span12Mux_s5_v.I +Span12Mux_s10_h.O Span12Mux_v.I +Span12Mux_s10_v.O LocalMux.I +Span12Mux_s10_v.O Sp12to4.I +Span12Mux_s10_v.O Span12Mux_s10_h.I +Span12Mux_s10_v.O Span12Mux_s5_v.I +Span12Mux_s10_v.O Span12Mux_s8_h.I +Span12Mux_s11_h.O LocalMux.I +Span12Mux_s11_h.O Sp12to4.I +Span12Mux_s11_h.O Span12Mux_s0_h.I +Span12Mux_s11_v.O LocalMux.I +Span12Mux_s11_v.O Sp12to4.I +Span12Mux_s11_v.O Span12Mux_s4_v.I +Span12Mux_s11_v.O Span12Mux_s8_h.I +Span12Mux_s11_v.O Span12Mux_s9_h.I +Span12Mux_s1_h.O LocalMux.I +Span12Mux_s1_h.O Sp12to4.I +Span12Mux_s1_h.O Span12Mux_s10_h.I +Span12Mux_s1_v.O LocalMux.I +Span12Mux_s1_v.O Sp12to4.I +Span12Mux_s1_v.O Span12Mux_v.I +Span12Mux_s2_h.O LocalMux.I +Span12Mux_s2_h.O Sp12to4.I +Span12Mux_s2_h.O Span12Mux_s0_v.I +Span12Mux_s2_h.O Span12Mux_s10_v.I +Span12Mux_s2_h.O Span12Mux_s11_v.I +Span12Mux_s2_h.O Span12Mux_s1_v.I +Span12Mux_s2_h.O Span12Mux_s2_v.I +Span12Mux_s2_h.O Span12Mux_s4_v.I +Span12Mux_s2_h.O Span12Mux_s6_v.I +Span12Mux_s2_h.O Span12Mux_s8_v.I +Span12Mux_s2_h.O Span12Mux_s9_h.I +Span12Mux_s2_h.O Span12Mux_s9_v.I +Span12Mux_s2_v.O LocalMux.I +Span12Mux_s2_v.O Sp12to4.I +Span12Mux_s2_v.O Span12Mux_s9_h.I +Span12Mux_s3_h.O LocalMux.I +Span12Mux_s3_h.O Sp12to4.I +Span12Mux_s3_h.O Span12Mux_s10_v.I +Span12Mux_s3_h.O Span12Mux_s11_v.I +Span12Mux_s3_h.O Span12Mux_s1_v.I +Span12Mux_s3_h.O Span12Mux_s2_v.I +Span12Mux_s3_h.O Span12Mux_s4_v.I +Span12Mux_s3_h.O Span12Mux_s6_v.I +Span12Mux_s3_h.O Span12Mux_s7_v.I +Span12Mux_s3_h.O Span12Mux_s8_h.I +Span12Mux_s3_h.O Span12Mux_s8_v.I +Span12Mux_s3_h.O Span12Mux_s9_v.I +Span12Mux_s3_h.O Span12Mux_v.I +Span12Mux_s3_v.O LocalMux.I +Span12Mux_s3_v.O Sp12to4.I +Span12Mux_s3_v.O Span12Mux_s8_h.I +Span12Mux_s3_v.O Span12Mux_v.I +Span12Mux_s4_h.O LocalMux.I +Span12Mux_s4_h.O Sp12to4.I +Span12Mux_s4_h.O Span12Mux_s2_v.I +Span12Mux_s4_h.O Span12Mux_s3_v.I +Span12Mux_s4_h.O Span12Mux_s4_v.I +Span12Mux_s4_h.O Span12Mux_s6_v.I +Span12Mux_s4_h.O Span12Mux_s7_h.I +Span12Mux_s4_h.O Span12Mux_s7_v.I +Span12Mux_s4_h.O Span12Mux_s8_v.I +Span12Mux_s4_v.O LocalMux.I +Span12Mux_s4_v.O Sp12to4.I +Span12Mux_s4_v.O Span12Mux_s10_h.I +Span12Mux_s4_v.O Span12Mux_s11_v.I +Span12Mux_s4_v.O Span12Mux_s2_h.I +Span12Mux_s4_v.O Span12Mux_s8_h.I +Span12Mux_s5_h.O LocalMux.I +Span12Mux_s5_h.O Sp12to4.I +Span12Mux_s5_h.O Span12Mux_s10_v.I +Span12Mux_s5_h.O Span12Mux_s11_v.I +Span12Mux_s5_h.O Span12Mux_s6_h.I +Span12Mux_s5_h.O Span12Mux_s7_v.I +Span12Mux_s5_h.O Span12Mux_s8_v.I +Span12Mux_s5_h.O Span12Mux_s9_v.I +Span12Mux_s5_h.O Span12Mux_v.I +Span12Mux_s5_v.O LocalMux.I +Span12Mux_s5_v.O Sp12to4.I +Span12Mux_s5_v.O Span12Mux_s10_h.I +Span12Mux_s5_v.O Span12Mux_s10_v.I +Span12Mux_s5_v.O Span12Mux_s5_h.I +Span12Mux_s5_v.O Span12Mux_s8_h.I +Span12Mux_s6_h.O LocalMux.I +Span12Mux_s6_h.O Sp12to4.I +Span12Mux_s6_h.O Span12Mux_s0_v.I +Span12Mux_s6_h.O Span12Mux_s11_v.I +Span12Mux_s6_h.O Span12Mux_s3_v.I +Span12Mux_s6_h.O Span12Mux_s5_h.I +Span12Mux_s6_h.O Span12Mux_s5_v.I +Span12Mux_s6_h.O Span12Mux_s7_v.I +Span12Mux_s6_h.O Span12Mux_s8_v.I +Span12Mux_s6_h.O Span12Mux_s9_v.I +Span12Mux_s6_h.O Span12Mux_v.I +Span12Mux_s6_v.O LocalMux.I +Span12Mux_s6_v.O Sp12to4.I +Span12Mux_s6_v.O Span12Mux_s5_h.I +Span12Mux_s6_v.O Span12Mux_s8_h.I +Span12Mux_s6_v.O Span12Mux_s9_v.I +Span12Mux_s7_h.O LocalMux.I +Span12Mux_s7_h.O Sp12to4.I +Span12Mux_s7_h.O Span12Mux_s10_v.I +Span12Mux_s7_h.O Span12Mux_s1_v.I +Span12Mux_s7_h.O Span12Mux_s4_h.I +Span12Mux_s7_h.O Span12Mux_s8_v.I +Span12Mux_s7_h.O Span12Mux_s9_v.I +Span12Mux_s7_h.O Span12Mux_v.I +Span12Mux_s7_v.O LocalMux.I +Span12Mux_s7_v.O Sp12to4.I +Span12Mux_s7_v.O Span12Mux_s10_h.I +Span12Mux_s7_v.O Span12Mux_s11_h.I +Span12Mux_s7_v.O Span12Mux_s6_h.I +Span12Mux_s7_v.O Span12Mux_s7_h.I +Span12Mux_s7_v.O Span12Mux_s8_h.I +Span12Mux_s7_v.O Span12Mux_s8_v.I +Span12Mux_s8_h.O LocalMux.I +Span12Mux_s8_h.O Sp12to4.I +Span12Mux_s8_h.O Span12Mux_s10_v.I +Span12Mux_s8_h.O Span12Mux_s11_v.I +Span12Mux_s8_h.O Span12Mux_s2_v.I +Span12Mux_s8_h.O Span12Mux_s3_h.I +Span12Mux_s8_h.O Span12Mux_s3_v.I +Span12Mux_s8_h.O Span12Mux_s4_v.I +Span12Mux_s8_h.O Span12Mux_s6_v.I +Span12Mux_s8_h.O Span12Mux_s7_v.I +Span12Mux_s8_h.O Span12Mux_s8_v.I +Span12Mux_s8_h.O Span12Mux_s9_v.I +Span12Mux_s8_h.O Span12Mux_v.I +Span12Mux_s8_v.O LocalMux.I +Span12Mux_s8_v.O Sp12to4.I +Span12Mux_s8_v.O Span12Mux_s10_h.I +Span12Mux_s8_v.O Span12Mux_s2_h.I +Span12Mux_s8_v.O Span12Mux_s7_v.I +Span12Mux_s8_v.O Span12Mux_s8_h.I +Span12Mux_s9_h.O LocalMux.I +Span12Mux_s9_h.O Sp12to4.I +Span12Mux_s9_h.O Span12Mux_s0_v.I +Span12Mux_s9_h.O Span12Mux_s10_v.I +Span12Mux_s9_h.O Span12Mux_s1_v.I +Span12Mux_s9_h.O Span12Mux_s2_h.I +Span12Mux_s9_h.O Span12Mux_s2_v.I +Span12Mux_s9_h.O Span12Mux_s4_v.I +Span12Mux_s9_h.O Span12Mux_v.I +Span12Mux_s9_v.O LocalMux.I +Span12Mux_s9_v.O Sp12to4.I +Span12Mux_s9_v.O Span12Mux_s6_v.I +Span12Mux_s9_v.O Span12Mux_s7_h.I +Span12Mux_v.O LocalMux.I +Span12Mux_v.O Sp12to4.I +Span12Mux_v.O Span12Mux_s0_h.I +Span12Mux_v.O Span12Mux_s0_v.I +Span12Mux_v.O Span12Mux_s10_h.I +Span12Mux_v.O Span12Mux_s11_h.I +Span12Mux_v.O Span12Mux_s1_h.I +Span12Mux_v.O Span12Mux_s1_v.I +Span12Mux_v.O Span12Mux_s2_h.I +Span12Mux_v.O Span12Mux_s2_v.I +Span12Mux_v.O Span12Mux_s3_h.I +Span12Mux_v.O Span12Mux_s3_v.I +Span12Mux_v.O Span12Mux_s4_h.I +Span12Mux_v.O Span12Mux_s5_h.I +Span12Mux_v.O Span12Mux_s6_h.I +Span12Mux_v.O Span12Mux_s7_h.I +Span12Mux_v.O Span12Mux_s8_h.I +Span12Mux_v.O Span12Mux_s9_h.I +Span4Mux_h.O LocalMux.I +Span4Mux_h.O Span4Mux_h.I +Span4Mux_h.O Span4Mux_s0_h.I +Span4Mux_h.O Span4Mux_s0_v.I +Span4Mux_h.O Span4Mux_s1_h.I +Span4Mux_h.O Span4Mux_s1_v.I +Span4Mux_h.O Span4Mux_s2_h.I +Span4Mux_h.O Span4Mux_s2_v.I +Span4Mux_h.O Span4Mux_s3_h.I +Span4Mux_h.O Span4Mux_s3_v.I +Span4Mux_h.O Span4Mux_v.I +Span4Mux_s0_h.O IoSpan4Mux.I +Span4Mux_s0_h.O LocalMux.I +Span4Mux_s0_h.O Span4Mux_h.I +Span4Mux_s0_h.O Span4Mux_s0_v.I +Span4Mux_s0_h.O Span4Mux_s1_v.I +Span4Mux_s0_h.O Span4Mux_s2_v.I +Span4Mux_s0_h.O Span4Mux_s3_v.I +Span4Mux_s0_h.O Span4Mux_v.I +Span4Mux_s0_v.O IoSpan4Mux.I +Span4Mux_s0_v.O LocalMux.I +Span4Mux_s0_v.O Span4Mux_h.I +Span4Mux_s0_v.O Span4Mux_s0_h.I +Span4Mux_s0_v.O Span4Mux_s1_h.I +Span4Mux_s0_v.O Span4Mux_s2_h.I +Span4Mux_s0_v.O Span4Mux_s3_h.I +Span4Mux_s0_v.O Span4Mux_v.I +Span4Mux_s1_h.O IoSpan4Mux.I +Span4Mux_s1_h.O LocalMux.I +Span4Mux_s1_h.O Span4Mux_h.I +Span4Mux_s1_h.O Span4Mux_s0_v.I +Span4Mux_s1_h.O Span4Mux_s1_v.I +Span4Mux_s1_h.O Span4Mux_s2_v.I +Span4Mux_s1_h.O Span4Mux_s3_v.I +Span4Mux_s1_h.O Span4Mux_v.I +Span4Mux_s1_v.O IoSpan4Mux.I +Span4Mux_s1_v.O LocalMux.I +Span4Mux_s1_v.O Span4Mux_h.I +Span4Mux_s1_v.O Span4Mux_s0_h.I +Span4Mux_s1_v.O Span4Mux_s1_h.I +Span4Mux_s1_v.O Span4Mux_s2_h.I +Span4Mux_s1_v.O Span4Mux_s3_h.I +Span4Mux_s1_v.O Span4Mux_v.I +Span4Mux_s2_h.O IoSpan4Mux.I +Span4Mux_s2_h.O LocalMux.I +Span4Mux_s2_h.O Span4Mux_h.I +Span4Mux_s2_h.O Span4Mux_s0_v.I +Span4Mux_s2_h.O Span4Mux_s1_v.I +Span4Mux_s2_h.O Span4Mux_s2_v.I +Span4Mux_s2_h.O Span4Mux_s3_v.I +Span4Mux_s2_h.O Span4Mux_v.I +Span4Mux_s2_v.O IoSpan4Mux.I +Span4Mux_s2_v.O LocalMux.I +Span4Mux_s2_v.O Span4Mux_h.I +Span4Mux_s2_v.O Span4Mux_s0_h.I +Span4Mux_s2_v.O Span4Mux_s1_h.I +Span4Mux_s2_v.O Span4Mux_s2_h.I +Span4Mux_s2_v.O Span4Mux_s3_h.I +Span4Mux_s2_v.O Span4Mux_v.I +Span4Mux_s3_h.O IoSpan4Mux.I +Span4Mux_s3_h.O LocalMux.I +Span4Mux_s3_h.O Span4Mux_h.I +Span4Mux_s3_h.O Span4Mux_s0_v.I +Span4Mux_s3_h.O Span4Mux_s1_v.I +Span4Mux_s3_h.O Span4Mux_s2_v.I +Span4Mux_s3_h.O Span4Mux_s3_v.I +Span4Mux_s3_h.O Span4Mux_v.I +Span4Mux_s3_v.O IoSpan4Mux.I +Span4Mux_s3_v.O LocalMux.I +Span4Mux_s3_v.O Span4Mux_h.I +Span4Mux_s3_v.O Span4Mux_s0_h.I +Span4Mux_s3_v.O Span4Mux_s1_h.I +Span4Mux_s3_v.O Span4Mux_s2_h.I +Span4Mux_s3_v.O Span4Mux_s3_h.I +Span4Mux_s3_v.O Span4Mux_v.I +Span4Mux_v.O LocalMux.I +Span4Mux_v.O Span4Mux_h.I +Span4Mux_v.O Span4Mux_s0_h.I +Span4Mux_v.O Span4Mux_s0_v.I +Span4Mux_v.O Span4Mux_s1_h.I +Span4Mux_v.O Span4Mux_s1_v.I +Span4Mux_v.O Span4Mux_s2_h.I +Span4Mux_v.O Span4Mux_s2_v.I +Span4Mux_v.O Span4Mux_s3_h.I +Span4Mux_v.O Span4Mux_s3_v.I +Span4Mux_v.O Span4Mux_v.I +VCC.Y IO_PAD.OE +VCC.Y PRE_IO.CLOCKENABLE +gio2CtrlBuf.O GlobalMux.I diff --git a/icefuzz/tmedges_8k.txt b/icefuzz/tmedges_8k.txt new file mode 100644 index 0000000..076886c --- /dev/null +++ b/icefuzz/tmedges_8k.txt @@ -0,0 +1,618 @@ +CEMux.O LogicCell40.ce +CEMux.O PRE_IO.CLOCKENABLE +CEMux.O SB_RAM40_4K.RCLKE +CEMux.O SB_RAM40_4K.WCLKE +CascadeMux.O LogicCell40.in2 +CascadeMux.O SB_RAM40_4K.RADDR[0] +CascadeMux.O SB_RAM40_4K.RADDR[10] +CascadeMux.O SB_RAM40_4K.RADDR[1] +CascadeMux.O SB_RAM40_4K.RADDR[2] +CascadeMux.O SB_RAM40_4K.RADDR[3] +CascadeMux.O SB_RAM40_4K.RADDR[4] +CascadeMux.O SB_RAM40_4K.RADDR[5] +CascadeMux.O SB_RAM40_4K.RADDR[6] +CascadeMux.O SB_RAM40_4K.RADDR[7] +CascadeMux.O SB_RAM40_4K.RADDR[8] +CascadeMux.O SB_RAM40_4K.RADDR[9] +CascadeMux.O SB_RAM40_4K.WADDR[0] +CascadeMux.O SB_RAM40_4K.WADDR[10] +CascadeMux.O SB_RAM40_4K.WADDR[1] +CascadeMux.O SB_RAM40_4K.WADDR[2] +CascadeMux.O SB_RAM40_4K.WADDR[3] +CascadeMux.O SB_RAM40_4K.WADDR[4] +CascadeMux.O SB_RAM40_4K.WADDR[5] +CascadeMux.O SB_RAM40_4K.WADDR[6] +CascadeMux.O SB_RAM40_4K.WADDR[7] +CascadeMux.O SB_RAM40_4K.WADDR[8] +CascadeMux.O SB_RAM40_4K.WADDR[9] +ClkMux.O INV.I +ClkMux.O LogicCell40.clk +ClkMux.O PRE_IO.INPUTCLK +ClkMux.O PRE_IO.OUTPUTCLK +ClkMux.O SB_RAM40_4K.RCLK +ClkMux.O SB_RAM40_4K.WCLK +GND.Y LogicCell40.carryin +GND.Y LogicCell40.clk +GND.Y LogicCell40.in0 +GND.Y LogicCell40.in1 +GND.Y LogicCell40.in2 +GND.Y LogicCell40.in3 +GND.Y LogicCell40.sr +GND.Y PRE_IO.DOUT0 +Glb2LocalMux.O LocalMux.I +GlobalMux.O CEMux.I +GlobalMux.O ClkMux.I +GlobalMux.O Glb2LocalMux.I +GlobalMux.O SRMux.I +ICE_CARRY_IN_MUX.carryinitout InMux.I +ICE_CARRY_IN_MUX.carryinitout LogicCell40.carryin +ICE_GB.GLOBALBUFFEROUTPUT gio2CtrlBuf.I +INV.O LogicCell40.clk +INV.O SB_RAM40_4K.RCLK +INV.O SB_RAM40_4K.WCLK +IO_PAD.DOUT PLL40.PLLIN +IO_PAD.DOUT PLL40_2.PLLIN +IO_PAD.DOUT PLL40_2F.PLLIN +IO_PAD.DOUT PRE_IO.PADIN +IO_PAD.DOUT PRE_IO_GBUF.PADSIGNALTOGLOBALBUFFER +IO_PAD.PACKAGEPIN IO_PAD.PACKAGEPIN +InMux.O CascadeMux.I +InMux.O LogicCell40.in0 +InMux.O LogicCell40.in1 +InMux.O LogicCell40.in3 +InMux.O SB_RAM40_4K.MASK[0] +InMux.O SB_RAM40_4K.MASK[10] +InMux.O SB_RAM40_4K.MASK[11] +InMux.O SB_RAM40_4K.MASK[12] +InMux.O SB_RAM40_4K.MASK[13] +InMux.O SB_RAM40_4K.MASK[14] +InMux.O SB_RAM40_4K.MASK[15] +InMux.O SB_RAM40_4K.MASK[1] +InMux.O SB_RAM40_4K.MASK[2] +InMux.O SB_RAM40_4K.MASK[3] +InMux.O SB_RAM40_4K.MASK[4] +InMux.O SB_RAM40_4K.MASK[5] +InMux.O SB_RAM40_4K.MASK[6] +InMux.O SB_RAM40_4K.MASK[7] +InMux.O SB_RAM40_4K.MASK[8] +InMux.O SB_RAM40_4K.MASK[9] +InMux.O SB_RAM40_4K.WDATA[0] +InMux.O SB_RAM40_4K.WDATA[10] +InMux.O SB_RAM40_4K.WDATA[11] +InMux.O SB_RAM40_4K.WDATA[12] +InMux.O SB_RAM40_4K.WDATA[13] +InMux.O SB_RAM40_4K.WDATA[14] +InMux.O SB_RAM40_4K.WDATA[15] +InMux.O SB_RAM40_4K.WDATA[1] +InMux.O SB_RAM40_4K.WDATA[2] +InMux.O SB_RAM40_4K.WDATA[3] +InMux.O SB_RAM40_4K.WDATA[4] +InMux.O SB_RAM40_4K.WDATA[5] +InMux.O SB_RAM40_4K.WDATA[6] +InMux.O SB_RAM40_4K.WDATA[7] +InMux.O SB_RAM40_4K.WDATA[8] +InMux.O SB_RAM40_4K.WDATA[9] +IoInMux.O ICE_GB.USERSIGNALTOGLOBALBUFFER +IoInMux.O PLL40.BYPASS +IoInMux.O PLL40.DYNAMICDELAY[0] +IoInMux.O PLL40.DYNAMICDELAY[1] +IoInMux.O PLL40.DYNAMICDELAY[2] +IoInMux.O PLL40.DYNAMICDELAY[3] +IoInMux.O PLL40.DYNAMICDELAY[4] +IoInMux.O PLL40.DYNAMICDELAY[5] +IoInMux.O PLL40.DYNAMICDELAY[6] +IoInMux.O PLL40.DYNAMICDELAY[7] +IoInMux.O PLL40.EXTFEEDBACK +IoInMux.O PLL40.LATCHINPUTVALUE +IoInMux.O PLL40.RESETB +IoInMux.O PLL40.SCLK +IoInMux.O PLL40.SDI +IoInMux.O PLL40_2.BYPASS +IoInMux.O PLL40_2.DYNAMICDELAY[0] +IoInMux.O PLL40_2.DYNAMICDELAY[1] +IoInMux.O PLL40_2.DYNAMICDELAY[2] +IoInMux.O PLL40_2.DYNAMICDELAY[3] +IoInMux.O PLL40_2.DYNAMICDELAY[4] +IoInMux.O PLL40_2.DYNAMICDELAY[5] +IoInMux.O PLL40_2.DYNAMICDELAY[6] +IoInMux.O PLL40_2.DYNAMICDELAY[7] +IoInMux.O PLL40_2.EXTFEEDBACK +IoInMux.O PLL40_2.LATCHINPUTVALUE +IoInMux.O PLL40_2.RESETB +IoInMux.O PLL40_2.SCLK +IoInMux.O PLL40_2.SDI +IoInMux.O PLL40_2F.BYPASS +IoInMux.O PLL40_2F.DYNAMICDELAY[0] +IoInMux.O PLL40_2F.DYNAMICDELAY[1] +IoInMux.O PLL40_2F.DYNAMICDELAY[2] +IoInMux.O PLL40_2F.DYNAMICDELAY[3] +IoInMux.O PLL40_2F.DYNAMICDELAY[4] +IoInMux.O PLL40_2F.DYNAMICDELAY[5] +IoInMux.O PLL40_2F.DYNAMICDELAY[6] +IoInMux.O PLL40_2F.DYNAMICDELAY[7] +IoInMux.O PLL40_2F.EXTFEEDBACK +IoInMux.O PLL40_2F.LATCHINPUTVALUE +IoInMux.O PLL40_2F.RESETB +IoInMux.O PLL40_2F.SCLK +IoInMux.O PLL40_2F.SDI +IoInMux.O PRE_IO.DOUT0 +IoInMux.O PRE_IO.DOUT1 +IoInMux.O PRE_IO.LATCHINPUTVALUE +IoInMux.O PRE_IO.OUTPUTENABLE +IoInMux.O SB_PLL40_2F_CORE.BYPASS +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[0] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[1] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[2] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[3] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[4] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[5] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[6] +IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[7] +IoInMux.O SB_PLL40_2F_CORE.EXTFEEDBACK +IoInMux.O SB_PLL40_2F_CORE.LATCHINPUTVALUE +IoInMux.O SB_PLL40_2F_CORE.REFERENCECLK +IoInMux.O SB_PLL40_2F_CORE.RESETB +IoInMux.O SB_PLL40_2F_CORE.SCLK +IoInMux.O SB_PLL40_2F_CORE.SDI +IoInMux.O SB_PLL40_CORE.BYPASS +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[0] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[1] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[2] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[3] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[4] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[5] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[6] +IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[7] +IoInMux.O SB_PLL40_CORE.EXTFEEDBACK +IoInMux.O SB_PLL40_CORE.LATCHINPUTVALUE +IoInMux.O SB_PLL40_CORE.REFERENCECLK +IoInMux.O SB_PLL40_CORE.RESETB +IoInMux.O SB_PLL40_CORE.SCLK +IoInMux.O SB_PLL40_CORE.SDI +IoSpan4Mux.O IoSpan4Mux.I +IoSpan4Mux.O LocalMux.I +IoSpan4Mux.O Span4Mux_h.I +IoSpan4Mux.O Span4Mux_s0_h.I +IoSpan4Mux.O Span4Mux_s0_v.I +IoSpan4Mux.O Span4Mux_s1_h.I +IoSpan4Mux.O Span4Mux_s1_v.I +IoSpan4Mux.O Span4Mux_s2_h.I +IoSpan4Mux.O Span4Mux_s2_v.I +IoSpan4Mux.O Span4Mux_s3_h.I +IoSpan4Mux.O Span4Mux_s3_v.I +IoSpan4Mux.O Span4Mux_v.I +LocalMux.O CEMux.I +LocalMux.O ClkMux.I +LocalMux.O InMux.I +LocalMux.O IoInMux.I +LocalMux.O SRMux.I +LogicCell40.carryout ICE_CARRY_IN_MUX.carryinitin +LogicCell40.carryout InMux.I +LogicCell40.carryout LogicCell40.carryin +LogicCell40.lcout LocalMux.I +LogicCell40.lcout Odrv12.I +LogicCell40.lcout Odrv4.I +LogicCell40.ltout CascadeMux.I +Odrv12.O LocalMux.I +Odrv12.O Sp12to4.I +Odrv12.O Span12Mux_h.I +Odrv12.O Span12Mux_s0_h.I +Odrv12.O Span12Mux_s0_v.I +Odrv12.O Span12Mux_s10_h.I +Odrv12.O Span12Mux_s10_v.I +Odrv12.O Span12Mux_s11_h.I +Odrv12.O Span12Mux_s11_v.I +Odrv12.O Span12Mux_s1_h.I +Odrv12.O Span12Mux_s1_v.I +Odrv12.O Span12Mux_s2_h.I +Odrv12.O Span12Mux_s2_v.I +Odrv12.O Span12Mux_s3_h.I +Odrv12.O Span12Mux_s3_v.I +Odrv12.O Span12Mux_s4_h.I +Odrv12.O Span12Mux_s4_v.I +Odrv12.O Span12Mux_s5_h.I +Odrv12.O Span12Mux_s5_v.I +Odrv12.O Span12Mux_s6_h.I +Odrv12.O Span12Mux_s6_v.I +Odrv12.O Span12Mux_s7_h.I +Odrv12.O Span12Mux_s7_v.I +Odrv12.O Span12Mux_s8_h.I +Odrv12.O Span12Mux_s8_v.I +Odrv12.O Span12Mux_s9_h.I +Odrv12.O Span12Mux_s9_v.I +Odrv12.O Span12Mux_v.I +Odrv4.O IoSpan4Mux.I +Odrv4.O LocalMux.I +Odrv4.O Span4Mux_h.I +Odrv4.O Span4Mux_s0_h.I +Odrv4.O Span4Mux_s0_v.I +Odrv4.O Span4Mux_s1_h.I +Odrv4.O Span4Mux_s1_v.I +Odrv4.O Span4Mux_s2_h.I +Odrv4.O Span4Mux_s2_v.I +Odrv4.O Span4Mux_s3_h.I +Odrv4.O Span4Mux_s3_v.I +Odrv4.O Span4Mux_v.I +PLL40.LOCK LocalMux.I +PLL40.PLLOUTCORE Odrv12.I +PLL40.PLLOUTGLOBAL GlobalMux.I +PLL40.SDO LocalMux.I +PLL40_2.LOCK LocalMux.I +PLL40_2.PLLOUTCOREA Odrv12.I +PLL40_2.PLLOUTCOREB Odrv12.I +PLL40_2.PLLOUTGLOBALA GlobalMux.I +PLL40_2.PLLOUTGLOBALB GlobalMux.I +PLL40_2.SDO LocalMux.I +PLL40_2F.LOCK LocalMux.I +PLL40_2F.PLLOUTCOREA Odrv12.I +PLL40_2F.PLLOUTCOREB Odrv12.I +PLL40_2F.PLLOUTGLOBALA GlobalMux.I +PLL40_2F.PLLOUTGLOBALB GlobalMux.I +PLL40_2F.SDO LocalMux.I +PRE_IO.DIN0 LocalMux.I +PRE_IO.DIN0 Odrv12.I +PRE_IO.DIN0 Odrv4.I +PRE_IO.DIN1 LocalMux.I +PRE_IO.DIN1 Odrv12.I +PRE_IO.DIN1 Odrv4.I +PRE_IO.PADOEN IO_PAD.OE +PRE_IO.PADOUT IO_PAD.DIN +PRE_IO_GBUF.GLOBALBUFFEROUTPUT gio2CtrlBuf.I +SB_PLL40_2F_CORE.LOCK LocalMux.I +SB_PLL40_2F_CORE.PLLOUTCOREA Odrv12.I +SB_PLL40_2F_CORE.PLLOUTCOREB Odrv12.I +SB_PLL40_2F_CORE.PLLOUTGLOBALA GlobalMux.I +SB_PLL40_2F_CORE.PLLOUTGLOBALB GlobalMux.I +SB_PLL40_2F_CORE.SDO LocalMux.I +SB_PLL40_CORE.LOCK LocalMux.I +SB_PLL40_CORE.PLLOUTCORE Odrv12.I +SB_PLL40_CORE.PLLOUTGLOBAL GlobalMux.I +SB_PLL40_CORE.SDO LocalMux.I +SB_RAM40_4K.RDATA[0] LocalMux.I +SB_RAM40_4K.RDATA[0] Odrv12.I +SB_RAM40_4K.RDATA[0] Odrv4.I +SB_RAM40_4K.RDATA[10] LocalMux.I +SB_RAM40_4K.RDATA[10] Odrv12.I +SB_RAM40_4K.RDATA[10] Odrv4.I +SB_RAM40_4K.RDATA[11] LocalMux.I +SB_RAM40_4K.RDATA[11] Odrv12.I +SB_RAM40_4K.RDATA[11] Odrv4.I +SB_RAM40_4K.RDATA[12] LocalMux.I +SB_RAM40_4K.RDATA[12] Odrv12.I +SB_RAM40_4K.RDATA[12] Odrv4.I +SB_RAM40_4K.RDATA[13] LocalMux.I +SB_RAM40_4K.RDATA[13] Odrv12.I +SB_RAM40_4K.RDATA[13] Odrv4.I +SB_RAM40_4K.RDATA[14] LocalMux.I +SB_RAM40_4K.RDATA[14] Odrv12.I +SB_RAM40_4K.RDATA[14] Odrv4.I +SB_RAM40_4K.RDATA[15] LocalMux.I +SB_RAM40_4K.RDATA[15] Odrv12.I +SB_RAM40_4K.RDATA[15] Odrv4.I +SB_RAM40_4K.RDATA[1] LocalMux.I +SB_RAM40_4K.RDATA[1] Odrv12.I +SB_RAM40_4K.RDATA[1] Odrv4.I +SB_RAM40_4K.RDATA[2] LocalMux.I +SB_RAM40_4K.RDATA[2] Odrv12.I +SB_RAM40_4K.RDATA[2] Odrv4.I +SB_RAM40_4K.RDATA[3] LocalMux.I +SB_RAM40_4K.RDATA[3] Odrv12.I +SB_RAM40_4K.RDATA[3] Odrv4.I +SB_RAM40_4K.RDATA[4] LocalMux.I +SB_RAM40_4K.RDATA[4] Odrv12.I +SB_RAM40_4K.RDATA[4] Odrv4.I +SB_RAM40_4K.RDATA[5] LocalMux.I +SB_RAM40_4K.RDATA[5] Odrv12.I +SB_RAM40_4K.RDATA[5] Odrv4.I +SB_RAM40_4K.RDATA[6] LocalMux.I +SB_RAM40_4K.RDATA[6] Odrv12.I +SB_RAM40_4K.RDATA[6] Odrv4.I +SB_RAM40_4K.RDATA[7] LocalMux.I +SB_RAM40_4K.RDATA[7] Odrv12.I +SB_RAM40_4K.RDATA[7] Odrv4.I +SB_RAM40_4K.RDATA[8] LocalMux.I +SB_RAM40_4K.RDATA[8] Odrv12.I +SB_RAM40_4K.RDATA[8] Odrv4.I +SB_RAM40_4K.RDATA[9] LocalMux.I +SB_RAM40_4K.RDATA[9] Odrv12.I +SB_RAM40_4K.RDATA[9] Odrv4.I +SRMux.O LogicCell40.sr +SRMux.O SB_RAM40_4K.RE +SRMux.O SB_RAM40_4K.WE +Sp12to4.O IoSpan4Mux.I +Sp12to4.O LocalMux.I +Sp12to4.O Span4Mux_h.I +Sp12to4.O Span4Mux_s0_h.I +Sp12to4.O Span4Mux_s0_v.I +Sp12to4.O Span4Mux_s1_h.I +Sp12to4.O Span4Mux_s1_v.I +Sp12to4.O Span4Mux_s2_h.I +Sp12to4.O Span4Mux_s2_v.I +Sp12to4.O Span4Mux_s3_h.I +Sp12to4.O Span4Mux_s3_v.I +Sp12to4.O Span4Mux_v.I +Span12Mux_h.O LocalMux.I +Span12Mux_h.O Sp12to4.I +Span12Mux_h.O Span12Mux_h.I +Span12Mux_h.O Span12Mux_s0_h.I +Span12Mux_h.O Span12Mux_s0_v.I +Span12Mux_h.O Span12Mux_s10_h.I +Span12Mux_h.O Span12Mux_s10_v.I +Span12Mux_h.O Span12Mux_s11_h.I +Span12Mux_h.O Span12Mux_s11_v.I +Span12Mux_h.O Span12Mux_s1_h.I +Span12Mux_h.O Span12Mux_s1_v.I +Span12Mux_h.O Span12Mux_s2_h.I +Span12Mux_h.O Span12Mux_s2_v.I +Span12Mux_h.O Span12Mux_s3_h.I +Span12Mux_h.O Span12Mux_s3_v.I +Span12Mux_h.O Span12Mux_s4_h.I +Span12Mux_h.O Span12Mux_s4_v.I +Span12Mux_h.O Span12Mux_s5_h.I +Span12Mux_h.O Span12Mux_s5_v.I +Span12Mux_h.O Span12Mux_s6_h.I +Span12Mux_h.O Span12Mux_s6_v.I +Span12Mux_h.O Span12Mux_s7_h.I +Span12Mux_h.O Span12Mux_s7_v.I +Span12Mux_h.O Span12Mux_s8_h.I +Span12Mux_h.O Span12Mux_s8_v.I +Span12Mux_h.O Span12Mux_s9_h.I +Span12Mux_h.O Span12Mux_s9_v.I +Span12Mux_h.O Span12Mux_v.I +Span12Mux_s0_h.O LocalMux.I +Span12Mux_s0_h.O Sp12to4.I +Span12Mux_s0_h.O Span12Mux_h.I +Span12Mux_s0_h.O Span12Mux_v.I +Span12Mux_s0_v.O LocalMux.I +Span12Mux_s0_v.O Sp12to4.I +Span12Mux_s0_v.O Span12Mux_h.I +Span12Mux_s0_v.O Span12Mux_v.I +Span12Mux_s10_h.O LocalMux.I +Span12Mux_s10_h.O Sp12to4.I +Span12Mux_s10_h.O Span12Mux_h.I +Span12Mux_s10_h.O Span12Mux_s10_v.I +Span12Mux_s10_h.O Span12Mux_s11_v.I +Span12Mux_s10_h.O Span12Mux_s4_v.I +Span12Mux_s10_h.O Span12Mux_s6_v.I +Span12Mux_s10_h.O Span12Mux_s8_v.I +Span12Mux_s10_h.O Span12Mux_s9_v.I +Span12Mux_s10_h.O Span12Mux_v.I +Span12Mux_s10_v.O LocalMux.I +Span12Mux_s10_v.O Sp12to4.I +Span12Mux_s10_v.O Span12Mux_h.I +Span12Mux_s10_v.O Span12Mux_s10_h.I +Span12Mux_s10_v.O Span12Mux_s7_h.I +Span12Mux_s10_v.O Span12Mux_s8_h.I +Span12Mux_s10_v.O Span12Mux_s9_h.I +Span12Mux_s10_v.O Span12Mux_v.I +Span12Mux_s11_h.O LocalMux.I +Span12Mux_s11_h.O Sp12to4.I +Span12Mux_s11_h.O Span12Mux_h.I +Span12Mux_s11_h.O Span12Mux_s10_v.I +Span12Mux_s11_h.O Span12Mux_s11_v.I +Span12Mux_s11_h.O Span12Mux_s9_v.I +Span12Mux_s11_h.O Span12Mux_v.I +Span12Mux_s11_v.O LocalMux.I +Span12Mux_s11_v.O Sp12to4.I +Span12Mux_s11_v.O Span12Mux_h.I +Span12Mux_s11_v.O Span12Mux_s8_h.I +Span12Mux_s11_v.O Span12Mux_s9_h.I +Span12Mux_s11_v.O Span12Mux_v.I +Span12Mux_s1_h.O LocalMux.I +Span12Mux_s1_h.O Sp12to4.I +Span12Mux_s1_h.O Span12Mux_h.I +Span12Mux_s1_h.O Span12Mux_s3_v.I +Span12Mux_s1_h.O Span12Mux_s6_v.I +Span12Mux_s1_h.O Span12Mux_s9_v.I +Span12Mux_s1_h.O Span12Mux_v.I +Span12Mux_s1_v.O LocalMux.I +Span12Mux_s1_v.O Sp12to4.I +Span12Mux_s1_v.O Span12Mux_v.I +Span12Mux_s2_h.O LocalMux.I +Span12Mux_s2_h.O Sp12to4.I +Span12Mux_s2_h.O Span12Mux_h.I +Span12Mux_s2_h.O Span12Mux_s11_v.I +Span12Mux_s2_h.O Span12Mux_s3_v.I +Span12Mux_s2_h.O Span12Mux_s9_v.I +Span12Mux_s2_h.O Span12Mux_v.I +Span12Mux_s2_v.O LocalMux.I +Span12Mux_s2_v.O Sp12to4.I +Span12Mux_s2_v.O Span12Mux_h.I +Span12Mux_s2_v.O Span12Mux_s2_h.I +Span12Mux_s2_v.O Span12Mux_s5_h.I +Span12Mux_s2_v.O Span12Mux_v.I +Span12Mux_s3_h.O LocalMux.I +Span12Mux_s3_h.O Sp12to4.I +Span12Mux_s3_h.O Span12Mux_h.I +Span12Mux_s3_h.O Span12Mux_s7_v.I +Span12Mux_s3_h.O Span12Mux_v.I +Span12Mux_s3_v.O LocalMux.I +Span12Mux_s3_v.O Sp12to4.I +Span12Mux_s3_v.O Span12Mux_h.I +Span12Mux_s3_v.O Span12Mux_v.I +Span12Mux_s4_h.O LocalMux.I +Span12Mux_s4_h.O Sp12to4.I +Span12Mux_s4_h.O Span12Mux_h.I +Span12Mux_s4_v.O LocalMux.I +Span12Mux_s4_v.O Sp12to4.I +Span12Mux_s4_v.O Span12Mux_h.I +Span12Mux_s4_v.O Span12Mux_v.I +Span12Mux_s5_h.O LocalMux.I +Span12Mux_s5_h.O Sp12to4.I +Span12Mux_s5_h.O Span12Mux_h.I +Span12Mux_s5_h.O Span12Mux_v.I +Span12Mux_s5_v.O LocalMux.I +Span12Mux_s5_v.O Sp12to4.I +Span12Mux_s5_v.O Span12Mux_h.I +Span12Mux_s5_v.O Span12Mux_v.I +Span12Mux_s6_h.O LocalMux.I +Span12Mux_s6_h.O Sp12to4.I +Span12Mux_s6_h.O Span12Mux_h.I +Span12Mux_s6_h.O Span12Mux_s10_v.I +Span12Mux_s6_h.O Span12Mux_s11_v.I +Span12Mux_s6_h.O Span12Mux_s6_v.I +Span12Mux_s6_h.O Span12Mux_v.I +Span12Mux_s6_v.O LocalMux.I +Span12Mux_s6_v.O Sp12to4.I +Span12Mux_s6_v.O Span12Mux_h.I +Span12Mux_s6_v.O Span12Mux_s10_h.I +Span12Mux_s6_v.O Span12Mux_s5_h.I +Span12Mux_s6_v.O Span12Mux_s7_h.I +Span12Mux_s6_v.O Span12Mux_s8_h.I +Span12Mux_s6_v.O Span12Mux_s9_h.I +Span12Mux_s6_v.O Span12Mux_v.I +Span12Mux_s7_h.O LocalMux.I +Span12Mux_s7_h.O Sp12to4.I +Span12Mux_s7_h.O Span12Mux_h.I +Span12Mux_s7_h.O Span12Mux_s10_v.I +Span12Mux_s7_h.O Span12Mux_s11_v.I +Span12Mux_s7_h.O Span12Mux_s4_v.I +Span12Mux_s7_h.O Span12Mux_s5_v.I +Span12Mux_s7_h.O Span12Mux_s6_v.I +Span12Mux_s7_h.O Span12Mux_s7_v.I +Span12Mux_s7_h.O Span12Mux_v.I +Span12Mux_s7_v.O LocalMux.I +Span12Mux_s7_v.O Sp12to4.I +Span12Mux_s7_v.O Span12Mux_h.I +Span12Mux_s7_v.O Span12Mux_v.I +Span12Mux_s8_h.O LocalMux.I +Span12Mux_s8_h.O Sp12to4.I +Span12Mux_s8_h.O Span12Mux_h.I +Span12Mux_s8_h.O Span12Mux_s10_v.I +Span12Mux_s8_h.O Span12Mux_s11_v.I +Span12Mux_s8_h.O Span12Mux_s4_v.I +Span12Mux_s8_h.O Span12Mux_s5_v.I +Span12Mux_s8_h.O Span12Mux_s6_v.I +Span12Mux_s8_h.O Span12Mux_s7_v.I +Span12Mux_s8_h.O Span12Mux_s8_v.I +Span12Mux_s8_h.O Span12Mux_s9_v.I +Span12Mux_s8_h.O Span12Mux_v.I +Span12Mux_s8_v.O LocalMux.I +Span12Mux_s8_v.O Sp12to4.I +Span12Mux_s8_v.O Span12Mux_h.I +Span12Mux_s8_v.O Span12Mux_s11_h.I +Span12Mux_s8_v.O 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