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-rw-r--r--docs/io_tile.html38
-rw-r--r--icefuzz/tests/sb_pll40_2_pad.v60
-rw-r--r--icefuzz/tests/sb_pll40_2f_core.v65
-rw-r--r--icefuzz/tests/sb_pll40_2f_pad.v65
-rw-r--r--icefuzz/tests/sb_pll40_core.v24
-rw-r--r--icefuzz/tests/sb_pll40_pad.v57
6 files changed, 273 insertions, 36 deletions
diff --git a/docs/io_tile.html b/docs/io_tile.html
index 3cbc045..53ee497 100644
--- a/docs/io_tile.html
+++ b/docs/io_tile.html
@@ -72,7 +72,7 @@ is first routed to one of 16 local tracks in the IO tile and then from the local
</p>
<p>
-The <tt>io_global/latch</tt> signal is shared among all IO tiles on an edge of the chip and is driven by <tt>wire_gbuf/in</tt>
+The <tt>io_global/latch</tt> signal is shared among all IO tiles on an edge of the chip and is driven by <tt>fabout</tt>
from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the <tt>io_global/latch</tt> signal are:
(0, 7), (13, 10), (5, 0), and (8, 17)
</p>
@@ -297,7 +297,7 @@ format to represent the corresponding configuration bits:
<p>
Signals internal to the FPGA can also be routed to the global nets. This is done by routing the signal
-to the <tt>wire_gbuf/in</tt> net on an IO tile. The same set of I/O tiles is used for this, but in this
+to the <tt>fabout</tt> net on an IO tile. The same set of I/O tiles is used for this, but in this
case each of the I/O tiles corresponds to a different global net:
</p>
@@ -345,7 +345,7 @@ IO columns.
<p>
The <tt>SB_WARMBOOT</tt> primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell
-are driven by the <tt>wire_gbuf/in</tt> signal from three IO tiles. In HX1K chips the tiles connected to the
+are driven by the <tt>fabout</tt> signal from three IO tiles. In HX1K chips the tiles connected to the
<tt>SB_WARMBOOT</tt> primitive are:
</p>
@@ -458,7 +458,7 @@ follows (bits listed from LSB to MSB):
</p>
<p>
-The PLL inputs are routed to the PLL via the <tt>wire_gbuf/in</tt> signal from various IO tiles. The non-clock
+The PLL inputs are routed to the PLL via the <tt>fabout</tt> signal from various IO tiles. The non-clock
PLL outputs are routed via otherwise unused <tt>neigh_op_*</tt> signals in fabric corners. For example in case
of the 1k chip:
</p>
@@ -466,23 +466,23 @@ of the 1k chip:
<p align="center">
<table cellpadding="3" border>
<tr><th>Tile</th><th>Net-Segment</th><th>SB_PLL40_* Port Name</th></tr>
-<tr><td>0 1</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>REFERENCECLK</tt></td></tr>
-<tr><td>0 2</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>EXTFEEDBACK</tt></td></tr>
-<tr><td>0 4</td><td><tt>wire_gbuf/in</tt></td><td rowspan="8"><tt>DYNAMICDELAY</tt></td></tr>
-<tr><td>0 5</td><td><tt>wire_gbuf/in</tt></td></tr>
-<tr><td>0 6</td><td><tt>wire_gbuf/in</tt></td></tr>
-<tr><td>0 10</td><td><tt>wire_gbuf/in</tt></td></tr>
-<tr><td>0 11</td><td><tt>wire_gbuf/in</tt></td></tr>
-<tr><td>0 12</td><td><tt>wire_gbuf/in</tt></td></tr>
-<tr><td>0 13</td><td><tt>wire_gbuf/in</tt></td></tr>
-<tr><td>0 14</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 1</td><td><tt>fabout</tt></td><td rowspan="1"><tt>REFERENCECLK</tt></td></tr>
+<tr><td>0 2</td><td><tt>fabout</tt></td><td rowspan="1"><tt>EXTFEEDBACK</tt></td></tr>
+<tr><td>0 4</td><td><tt>fabout</tt></td><td rowspan="8"><tt>DYNAMICDELAY</tt></td></tr>
+<tr><td>0 5</td><td><tt>fabout</tt></td></tr>
+<tr><td>0 6</td><td><tt>fabout</tt></td></tr>
+<tr><td>0 10</td><td><tt>fabout</tt></td></tr>
+<tr><td>0 11</td><td><tt>fabout</tt></td></tr>
+<tr><td>0 12</td><td><tt>fabout</tt></td></tr>
+<tr><td>0 13</td><td><tt>fabout</tt></td></tr>
+<tr><td>0 14</td><td><tt>fabout</tt></td></tr>
<tr><td>1 1</td><td><tt>neigh_op_bnl_1</tt></td><td rowspan="1"><tt>LOCK</tt></td></tr>
-<tr><td>1 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>BYPASS</tt></td></tr>
-<tr><td>2 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>RESETB</tt></td></tr>
-<tr><td>5 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>LATCHINPUTVALUE</tt></td></tr>
+<tr><td>1 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>BYPASS</tt></td></tr>
+<tr><td>2 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>RESETB</tt></td></tr>
+<tr><td>5 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>LATCHINPUTVALUE</tt></td></tr>
<tr><td>12 1</td><td><tt>neigh_op_bnl_1</tt></td><td rowspan="1"><tt>SDO</tt></td></tr>
-<tr><td>4 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>SDI</tt></td></tr>
-<tr><td>5 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>SCLK</tt></td></tr>
+<tr><td>4 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>SDI</tt></td></tr>
+<tr><td>5 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>SCLK</tt></td></tr>
</table>
</p>
diff --git a/icefuzz/tests/sb_pll40_2_pad.v b/icefuzz/tests/sb_pll40_2_pad.v
new file mode 100644
index 0000000..4137a22
--- /dev/null
+++ b/icefuzz/tests/sb_pll40_2_pad.v
@@ -0,0 +1,60 @@
+module top(
+ input PACKAGEPIN,
+ output [1:0] PLLOUTCORE,
+ output [1:0] PLLOUTGLOBAL,
+ input EXTFEEDBACK,
+ input [7:0] DYNAMICDELAY,
+ output LOCK,
+ input BYPASS,
+ input RESETB,
+ input LATCHINPUTVALUE,
+
+ //Test Pins
+ output SDO,
+ input SDI,
+ input SCLK
+);
+ SB_PLL40_2_PAD #(
+ .FEEDBACK_PATH("DELAY"),
+ // .FEEDBACK_PATH("SIMPLE"),
+ // .FEEDBACK_PATH("PHASE_AND_DELAY"),
+ // .FEEDBACK_PATH("EXTERNAL"),
+
+ .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
+ // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
+
+ .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
+ // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
+
+ .PLLOUT_SELECT_PORTB("GENCLK"),
+ // .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
+
+ .SHIFTREG_DIV_MODE(1'b0),
+ .FDA_FEEDBACK(4'b1111),
+ .FDA_RELATIVE(4'b1111),
+ .DIVR(4'b0000),
+ .DIVF(7'b0000000),
+ .DIVQ(3'b001),
+ .FILTER_RANGE(3'b000),
+ .ENABLE_ICEGATE_PORTA(1'b0),
+ .ENABLE_ICEGATE_PORTB(1'b0),
+ .TEST_MODE(1'b0)
+ ) uut (
+ .PACKAGEPIN (PACKAGEPIN ),
+ .PLLOUTCOREA (PLLOUTCORE [0]),
+ .PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
+ .PLLOUTCOREB (PLLOUTCORE [1]),
+ .PLLOUTGLOBALB (PLLOUTGLOBAL[1]),
+ .EXTFEEDBACK (EXTFEEDBACK ),
+ .DYNAMICDELAY (DYNAMICDELAY ),
+ .LOCK (LOCK ),
+ .BYPASS (BYPASS ),
+ .RESETB (RESETB ),
+ .LATCHINPUTVALUE(LATCHINPUTVALUE),
+ .SDO (SDO ),
+ .SDI (SDI ),
+ .SCLK (SCLK )
+ );
+endmodule
diff --git a/icefuzz/tests/sb_pll40_2f_core.v b/icefuzz/tests/sb_pll40_2f_core.v
new file mode 100644
index 0000000..8055e12
--- /dev/null
+++ b/icefuzz/tests/sb_pll40_2f_core.v
@@ -0,0 +1,65 @@
+module top(
+ input REFERENCECLK,
+ output [1:0] PLLOUTCORE,
+ output [1:0] PLLOUTGLOBAL,
+ input EXTFEEDBACK,
+ input [7:0] DYNAMICDELAY,
+ output LOCK,
+ input BYPASS,
+ input RESETB,
+ input LATCHINPUTVALUE,
+
+ //Test Pins
+ output SDO,
+ input SDI,
+ input SCLK
+);
+ SB_PLL40_2F_CORE #(
+ .FEEDBACK_PATH("DELAY"),
+ // .FEEDBACK_PATH("SIMPLE"),
+ // .FEEDBACK_PATH("PHASE_AND_DELAY"),
+ // .FEEDBACK_PATH("EXTERNAL"),
+
+ .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
+ // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
+
+ .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
+ // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
+
+ .PLLOUT_SELECT_PORTA("GENCLK"),
+ // .PLLOUT_SELECT_PORTA("GENCLK_HALF"),
+ // .PLLOUT_SELECT_PORTA("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"),
+
+ .PLLOUT_SELECT_PORTB("GENCLK"),
+ // .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
+
+ .SHIFTREG_DIV_MODE(1'b0),
+ .FDA_FEEDBACK(4'b1111),
+ .FDA_RELATIVE(4'b1111),
+ .DIVR(4'b0000),
+ .DIVF(7'b0000000),
+ .DIVQ(3'b001),
+ .FILTER_RANGE(3'b000),
+ .ENABLE_ICEGATE_PORTA(1'b0),
+ .ENABLE_ICEGATE_PORTB(1'b0),
+ .TEST_MODE(1'b0)
+ ) uut (
+ .REFERENCECLK (REFERENCECLK ),
+ .PLLOUTCOREA (PLLOUTCORE [0]),
+ .PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
+ .PLLOUTCOREB (PLLOUTCORE [1]),
+ .PLLOUTGLOBALB (PLLOUTGLOBAL[1]),
+ .EXTFEEDBACK (EXTFEEDBACK ),
+ .DYNAMICDELAY (DYNAMICDELAY ),
+ .LOCK (LOCK ),
+ .BYPASS (BYPASS ),
+ .RESETB (RESETB ),
+ .LATCHINPUTVALUE(LATCHINPUTVALUE),
+ .SDO (SDO ),
+ .SDI (SDI ),
+ .SCLK (SCLK )
+ );
+endmodule
diff --git a/icefuzz/tests/sb_pll40_2f_pad.v b/icefuzz/tests/sb_pll40_2f_pad.v
new file mode 100644
index 0000000..65bfad4
--- /dev/null
+++ b/icefuzz/tests/sb_pll40_2f_pad.v
@@ -0,0 +1,65 @@
+module top(
+ input PACKAGEPIN,
+ output [1:0] PLLOUTCORE,
+ output [1:0] PLLOUTGLOBAL,
+ input EXTFEEDBACK,
+ input [7:0] DYNAMICDELAY,
+ output LOCK,
+ input BYPASS,
+ input RESETB,
+ input LATCHINPUTVALUE,
+
+ //Test Pins
+ output SDO,
+ input SDI,
+ input SCLK
+);
+ SB_PLL40_2F_PAD #(
+ .FEEDBACK_PATH("DELAY"),
+ // .FEEDBACK_PATH("SIMPLE"),
+ // .FEEDBACK_PATH("PHASE_AND_DELAY"),
+ // .FEEDBACK_PATH("EXTERNAL"),
+
+ .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
+ // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
+
+ .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
+ // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
+
+ .PLLOUT_SELECT_PORTA("GENCLK"),
+ // .PLLOUT_SELECT_PORTA("GENCLK_HALF"),
+ // .PLLOUT_SELECT_PORTA("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"),
+
+ .PLLOUT_SELECT_PORTB("GENCLK"),
+ // .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
+
+ .SHIFTREG_DIV_MODE(1'b0),
+ .FDA_FEEDBACK(4'b1111),
+ .FDA_RELATIVE(4'b1111),
+ .DIVR(4'b0000),
+ .DIVF(7'b0000000),
+ .DIVQ(3'b001),
+ .FILTER_RANGE(3'b000),
+ .ENABLE_ICEGATE_PORTA(1'b0),
+ .ENABLE_ICEGATE_PORTB(1'b0),
+ .TEST_MODE(1'b0)
+ ) uut (
+ .PACKAGEPIN (PACKAGEPIN ),
+ .PLLOUTCOREA (PLLOUTCORE [0]),
+ .PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
+ .PLLOUTCOREB (PLLOUTCORE [1]),
+ .PLLOUTGLOBALB (PLLOUTGLOBAL[1]),
+ .EXTFEEDBACK (EXTFEEDBACK ),
+ .DYNAMICDELAY (DYNAMICDELAY ),
+ .LOCK (LOCK ),
+ .BYPASS (BYPASS ),
+ .RESETB (RESETB ),
+ .LATCHINPUTVALUE(LATCHINPUTVALUE),
+ .SDO (SDO ),
+ .SDI (SDI ),
+ .SCLK (SCLK )
+ );
+endmodule
diff --git a/icefuzz/tests/sb_pll40_core.v b/icefuzz/tests/sb_pll40_core.v
index 298fb73..9954eca 100644
--- a/icefuzz/tests/sb_pll40_core.v
+++ b/icefuzz/tests/sb_pll40_core.v
@@ -1,7 +1,7 @@
module top(
input REFERENCECLK,
- output [1:0] PLLOUTCORE,
- output [1:0] PLLOUTGLOBAL,
+ output PLLOUTCORE,
+ output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
@@ -14,7 +14,7 @@ module top(
input SDI,
input SCLK
);
- SB_PLL40_2F_CORE #(
+ SB_PLL40_CORE #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
@@ -26,10 +26,7 @@ module top(
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
- .PLLOUT_SELECT_PORTA("GENCLK"),
- .PLLOUT_SELECT_PORTB("GENCLK"),
-
- // .PLLOUT_SELECT("GENCLK"),
+ .PLLOUT_SELECT("GENCLK"),
// .PLLOUT_SELECT("GENCLK_HALF"),
// .PLLOUT_SELECT("SHIFTREG_90deg"),
// .PLLOUT_SELECT("SHIFTREG_0deg"),
@@ -41,19 +38,12 @@ module top(
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
- // .ENABLE_ICEGATE(1'b0),
- .ENABLE_ICEGATE_PORTA(1'b0),
- .ENABLE_ICEGATE_PORTB(1'b0),
+ .ENABLE_ICEGATE(1'b0),
.TEST_MODE(1'b0)
) uut (
.REFERENCECLK (REFERENCECLK ),
- // .PACKAGEPIN (REFERENCECLK ),
- // .PLLOUTCORE (PLLOUTCORE ),
- // .PLLOUTGLOBAL (PLLOUTGLOBAL ),
- .PLLOUTCOREA (PLLOUTCORE [0]),
- .PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
- .PLLOUTCOREB (PLLOUTCORE [1]),
- .PLLOUTGLOBALB (PLLOUTGLOBAL[1]),
+ .PLLOUTCORE (PLLOUTCORE ),
+ .PLLOUTGLOBAL (PLLOUTGLOBAL ),
.EXTFEEDBACK (EXTFEEDBACK ),
.DYNAMICDELAY (DYNAMICDELAY ),
.LOCK (LOCK ),
diff --git a/icefuzz/tests/sb_pll40_pad.v b/icefuzz/tests/sb_pll40_pad.v
new file mode 100644
index 0000000..180d04b
--- /dev/null
+++ b/icefuzz/tests/sb_pll40_pad.v
@@ -0,0 +1,57 @@
+module top(
+ input PACKAGEPIN,
+ output PLLOUTCORE,
+ output PLLOUTGLOBAL,
+ input EXTFEEDBACK,
+ input [7:0] DYNAMICDELAY,
+ output LOCK,
+ input BYPASS,
+ input RESETB,
+ input LATCHINPUTVALUE,
+
+ //Test Pins
+ output SDO,
+ input SDI,
+ input SCLK
+);
+ SB_PLL40_PAD #(
+ .FEEDBACK_PATH("DELAY"),
+ // .FEEDBACK_PATH("SIMPLE"),
+ // .FEEDBACK_PATH("PHASE_AND_DELAY"),
+ // .FEEDBACK_PATH("EXTERNAL"),
+
+ .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
+ // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
+
+ .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
+ // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
+
+ .PLLOUT_SELECT("GENCLK"),
+ // .PLLOUT_SELECT("GENCLK_HALF"),
+ // .PLLOUT_SELECT("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT("SHIFTREG_0deg"),
+
+ .SHIFTREG_DIV_MODE(1'b0),
+ .FDA_FEEDBACK(4'b1111),
+ .FDA_RELATIVE(4'b1111),
+ .DIVR(4'b0000),
+ .DIVF(7'b0000000),
+ .DIVQ(3'b001),
+ .FILTER_RANGE(3'b000),
+ .ENABLE_ICEGATE(1'b0),
+ .TEST_MODE(1'b0)
+ ) uut (
+ .PACKAGEPIN (PACKAGEPIN ),
+ .PLLOUTCORE (PLLOUTCORE ),
+ .PLLOUTGLOBAL (PLLOUTGLOBAL ),
+ .EXTFEEDBACK (EXTFEEDBACK ),
+ .DYNAMICDELAY (DYNAMICDELAY ),
+ .LOCK (LOCK ),
+ .BYPASS (BYPASS ),
+ .RESETB (RESETB ),
+ .LATCHINPUTVALUE(LATCHINPUTVALUE),
+ .SDO (SDO ),
+ .SDI (SDI ),
+ .SCLK (SCLK )
+ );
+endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-24 03:34:10 +0000