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+++ b/docs/index.html
@@ -101,6 +101,11 @@ Here is a list of currently supported parts and the corresponding options for ar
</table>
<p>
+ Experimental support is also included for one iCE40 UltraPlus device, the iCE40-UP5K-SG48, including support for some of
+ the new UltraPlus features such as DSPs, SPRAM and internal oscillators.
+</p>
+
+<p>
Current work focuses on further improving our timing analysis flow.
</p>
@@ -309,6 +314,8 @@ The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.
<li><a href="format.html">The Bitstream File Format</a></li>
<li><a href="bitdocs-1k/">The iCE40 HX1K Bit Docs</a></li>
<li><a href="bitdocs-8k/">The iCE40 HX8K Bit Docs</a></li>
+<li><a href="ultraplus.html">Notes on UltraPlus features</a></li>
+
</ul>
<p>
diff --git a/docs/ultraplus.html b/docs/ultraplus.html
new file mode 100644
index 0000000..da109b5
--- /dev/null
+++ b/docs/ultraplus.html
@@ -0,0 +1,267 @@
+<!DOCTYPE html>
+<html><head><meta charset="UTF-8">
+<style>
+.ctab {
+ margin-left: auto;
+ margin-right: auto;
+ border: 1px solid gray;
+}
+.ctab td, .ctab th {
+ padding: 3px;
+ border: 1px solid gray;
+}
+
+.ctab td {
+ font-family:monospace;
+}
+</style>
+<title>Project IceStorm &ndash; UltraPlus Features Documentation</title>
+</head><body>
+<h1>Project IceStorm &ndash; UltraPlus Features Documentation</h1>
+
+<p>
+<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+This is work in progress.</i>
+</p>
+
+<p>The ice40 UltraPlus devices have a number of new features compared to the older LP/HX series
+ devices, in particular:
+ <ul>
+ <li>Internal DSP units, capable of 16-bit multiply and 32-bit accumulate.</li>
+ <li>1Mbit of extra single-ported RAM, in addition to the usual BRAM</li>
+ <li>Internal hard IP cores for I2C and SPI</li>
+ <li>2 internal oscillators, 48MHz (with divider) and 10kHz</li>
+ <li>24mA constant current LED ouputs and PWM hard IP</li>
+ </ul>
+ In order to implement these new features, a significant architecural change has been made: the
+ left and right sides of the device are no longer IO, but instead DSP and IPConnect tiles.
+
+</p>
+
+<p>Currently icestorm and arachne-pnr support the DSPs (except for cascading), SPRAM , internal oscillators and constant current
+ LED drivers. Work to support the remaining features is underway.</p>
+
+<h2>DSP Tiles</h2>
+<p>Each MAC16 DSP comprises of 4 DSP tiles, all of which perform part of the DSP function and have
+different routing bit configurations. Structually they are similar to logic tiles, but with the DSP
+function wired into where the LUTs and DFFs would be. The four types of DSP tiles will be referred to
+as DSP0 through DSP3, with DSP0 at the lowest y-position. One signal CO, is also routed through the
+IPConnect tile above the DSP tile, referred to as IPCON4 in this context.
+
+The location of signals and configuration bits is documented below.</p>
+<p>
+<strong>Signal Assignments</strong><br/>
+<table class="ctab">
+<tr><th>SB_MAC16 port</th><th>DSP0</th><th>DSP1</th><th>DSP2</th><th>DSP3</th><th>IPCON4</th></tr>
+
+<tr><td>CLK</td><td>-</td><td>-</td><td>lutff_global/clk</td><td>-</td><td>-</td></tr>
+
+<tr><td>CE</td><td>-</td><td>-</td><td>lutff_global/cen</td><td>-</td><td>-</td></tr>
+
+
+<tr><td>C[7:0]</td><td>-</td><td>-</td><td>-</td><td>lutff_[7:0]/in_3</td><td>-</td></tr>
+<tr><td>C[15:8]</td><td>-</td><td>-</td><td>-</td><td>lutff_[7:0]/in_1</td><td>-</td></tr>
+
+<tr><td>A[7:0]</td><td>-</td><td>-</td><td>lutff_[7:0]/in_3</td><td>-</td><td>-</td></tr>
+<tr><td>A[15:8]</td><td>-</td><td>-</td><td>lutff_[7:0]/in_1</td><td>-</td><td>-</td></tr>
+
+<tr><td>B[7:0]</td><td>-</td><td>lutff_[7:0]/in_3</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>B[15:8]</td><td>-</td><td>lutff_[7:0]/in_1</td><td>-</td><td>-</td><td>-</td></tr>
+
+<tr><td>D[7:0]</td><td>lutff_[7:0]/in_3</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>D[15:8]</td><td>lutff_[7:0]/in_1</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+
+<tr><td>IRSTTOP</td><td>-</td><td>lutff_global/s_r</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>IRSTBOT</td><td>lutff_global/s_r</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>ORSTTOP</td><td>-</td><td>-</td><td>-</td><td>lutff_global/s_r</td><td>-</td></tr>
+<tr><td>ORSTBOT</td><td>-</td><td>-</td><td>lutff_global/s_r</td><td>-</td><td>-</td></tr>
+
+
+
+<tr><td>AHOLD</td><td>-</td><td>-</td><td>lutff_0/in_0</td><td>-</td><td>-</td></tr>
+<tr><td>BHOLD</td><td>-</td><td>lutff_0/in_0</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>CHOLD</td><td>-</td><td>-</td><td>-</td><td>lutff_0/in_0</td><td>-</td></tr>
+<tr><td>DHOLD</td><td>lutff_0/in_0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+
+<tr><td>OHOLDTOP</td><td>-</td><td>-</td><td>-</td><td>lutff_1/in_0</td><td>-</td></tr>
+<tr><td>OHOLDBOT</td><td>lutff_1/in_0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+
+
+<tr><td>ADDSUBTOP</td><td>-</td><td>-</td><td>-</td><td>lutff_3/in_0</td><td>-</td></tr>
+<tr><td>ADDSUBBOT</td><td>lutff_3/in_0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+
+
+<tr><td>OLOADTOP</td><td>-</td><td>-</td><td>-</td><td>lutff_2/in_0</td><td>-</td></tr>
+<tr><td>OLOADBOT</td><td>lutff_2/in_0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+
+<tr><td>CI</td><td>lutff_4/in_0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+
+
+<tr><td>O[31:0]</td><td>mult/O_[7:0]</td><td>mult/O_[15:8]</td><td>mult/O_[23:16]</td><td>mult/O_[31:24]</td><td>-</td></tr>
+<tr><td>CO</td><td>-</td><td>-</td><td>-</td><td>-</td><td>slf_op_0</td></tr>
+
+</table>
+
+
+</p>
+
+<p>
+<strong>Configuration Bits</strong><br/>
+<p>The DSP configuration bits mostly follow the order stated in the ICE Technology Library document, where they are described as <span style="font-family:monospace">CBIT[24:0]</span>. For most DSP tiles,
+ these follow a logical order where <span style="font-family:monospace">CBIT[7:0]</span> maps to DSP0 <span style="font-family:monospace">CBIT[7:0]</span>; <span style="font-family:monospace">CBIT[15:8]</span>
+ to DSP1 <span style="font-family:monospace">CBIT[7:0]</span>, <span style="font-family:monospace">CBIT[23:16]</span> to DSP2 <span style="font-family:monospace">CBIT[7:0]</span>
+ and <span style="font-family:monospace">CBIT[24]</span> to DSP3 <span style="font-family:monospace">CBIT0</span>.
+ </p>
+<p>However, there is one location where configuration bits are swapped between DSP tiles and IPConnect tiles. In DSP1 (0, 16) <span style="font-family:monospace">CBIT[4:1]</span> are used
+ for IP such as the internal oscillator, and the DSP configuration bits are then located in IPConnect tile (0, 19) <span style="font-family:monospace">CBIT[6:3]</span>.</p>
+<p>The full list of configuration bits, including the changes for the DSP at (0, 15) are described in the table below.</p>
+
+<table class="ctab">
+<tr><th>Parameter</th><th>Normal Position</th><th>DSP (0, 15)<br/>Changes</th></tr>
+<tr><td>C_REG</td><td>DSP0.CBIT_0</td><td></td></tr>
+<tr><td>A_REG</td><td>DSP0.CBIT_1</td><td></td></tr>
+<tr><td>B_REG</td><td>DSP0.CBIT_2</td><td></td></tr>
+<tr><td>D_REG</td><td>DSP0.CBIT_3</td><td></td></tr>
+
+<tr><td>TOP_8x8_MULT_REG</td><td>DSP0.CBIT_4</td><td></td></tr>
+<tr><td>BOT_8x8_MULT_REG</td><td>DSP0.CBIT_5</td><td></td></tr>
+
+<tr><td>PIPELINE_16x16_MULT_REG1</td><td>DSP0.CBIT_6</td><td></td></tr>
+<tr><td>PIPELINE_16x16_MULT_REG2</td><td>DSP0.CBIT_7</td><td></td></tr>
+
+<tr><td>TOPOUTPUT_SELECT[0]</td><td>DSP1.CBIT_0</td><td></td></tr>
+<tr><td>TOPOUTPUT_SELECT[1]</td><td>DSP1.CBIT_1</td><td>(0, 19).CBIT_3</td></tr>
+
+<tr><td>TOPADDSUB_LOWERINPUT[1:0]</td><td>DSP1.CBIT_[3:2]</td><td>(0, 19).CBIT_[5:4]</td></tr>
+<tr><td>TOPADDSUB_UPPERINUT</td><td>DSP1.CBIT_4</td><td>(0, 19).CBIT_6</td></tr>
+<tr><td>TOPADDSUB_CARRYSELECT[1:0]</td><td>DSP1.CBIT_[6:5]</td><td></td></tr>
+
+<tr><td>BOTOUTPUT_SELECT[0]</td><td>DSP1.CBIT_7</td><td></td></tr>
+<tr><td>BOTOUTPUT_SELECT[1]</td><td>DSP2.CBIT_0</td><td></td></tr>
+
+<tr><td>BOTADDSUB_LOWERINPUT[1:0]</td><td>DSP2.CBIT_[2:1]</td><td></td></tr>
+<tr><td>BOTADDSUB_UPPERINPUT</td><td>DSP2.CBIT_3</td><td></td></tr>
+<tr><td>BOTADDSUB_CARRYSELECT[1:0]</td><td>DSP2.CBIT_[5:4]</td><td></td></tr>
+
+<tr><td>MODE_8x8</td><td>DSP2.CBIT_6</td><td></td></tr>
+
+<tr><td>A_SIGNED</td><td>DSP2.CBIT_7</td><td></td></tr>
+<tr><td>B_SIGNED</td><td>DSP3.CBIT_0</td><td></td></tr>
+
+</table>
+
+<p>Lattice document a limited number of supported configurations in the ICE Technology Library document, and Lattice's EDIF parser will
+ reject designs not following a supported configuration. It is not yet known whether unsupported configurations (such as mixed
+ signed and unsigned) function correctly or not.
+
+<p>
+<strong>Other Implementation Notes</strong><br/>
+<p>
+ All active DSP tiles, and all IPConnect tiles whether used or not, have some bits set which reflect their logic tile heritage. The <span style="font-family:monospace">LC_<em>x</em></span>
+ bits which would be used to configure the logic cell, are set to the below pattern for each "logic cell" (interpreting them like a logic tile):<br/>
+ <br><span style="font-family:monospace">0000111100001111 0000</span><br/><br/>
+ Coincidentally or not, this corresponds to a buffer passing through input 2 to the output. For each "cell" the cascade bit <span style="font-family:monospace">LC0<em>x</em>_inmux02_5</span> is
+ also set, effectively creating one large chain, as this connects input 2 to the output of the previous LUT. The DSPs at least will not function unless these bits are set correctly, so they <!DOCTYPE html>
+ have some purpose and presumably indicate that the remains of a LUT are still present. There does not seem to be any case under which iCEcube generates a pattern other than this though.
+</p>
+</p>
+<h2>IPConnect Tiles</h2>
+<p>IPConnect tiles are used for connections to all of the other UltraPlus features, such as I2C/SPI, SPRAM, RGB and oscillators. Like DSP tiles,
+they are structually similar to logic tiles. The outputs of IP functions are connected to nets named <span style="font-family:monospace">slf_op_0</span> through <span style="font-family:monospace">slf_op_7</span>,
+and the inputs use the LUT/FF inputs in the same way as DSP tiles.</p>
+
+
+
+<h2>Internal Oscillators</h2>
+
+Both of the internal oscillators are connected through IPConnect tiles, with their outputs optionally connected to the global networks,
+by setting the "padin" extra bit (the used global networks 4 and 5 don't have physical pins on UltraPlus devices).
+
+<h3>SB_HFOSC</h3>
+<p>The <span style="font-family:monospace">CLKHFPU</span> input connects through IPConnect tile (0, 29) input <span style="font-family:monospace">lutff_0/in_1</span>;
+and the <span style="font-family:monospace">CLKHFEN</span> input connects through input <span style="font-family:monospace">lutff_7/in_3</span> of the same tile.<br/>
+
+The <span style="font-family:monospace">CLKHF</span> output of SB_HFOSC is connected to both IPConnect tile (0, 28) output <span style="font-family:monospace">slf_op_7</span> and to the <span style="font-family:monospace">padin</span>
+ of <span style="font-family:monospace">glb_netwk_4</span>.</p>
+
+<p>Configuration bit <span style="font-family:monospace">CLKHF_DIV[1]</span> maps to DSP1 tile (0, 16) config bit <span style="font-family:monospace">CBIT_4</span>, and
+<span style="font-family:monospace">CLKHF_DIV[0]</span> maps to DSP1 tile (0, 16) config bit <span style="font-family:monospace">CBIT_3</span>.</p>
+
+<h3>SB_LFOSC</h3>
+<p>The <span style="font-family:monospace">CLKLFPU</span> input connects through IPConnect tile (25, 29) input <span style="font-family:monospace">lutff_0/in_1</span>;
+and the <span style="font-family:monospace">CLKLFEN</span> input connects through input <span style="font-family:monospace">lutff_7/in_3</span> of the same tile.<br/>
+
+The <span style="font-family:monospace">CLKLF</span> output of SB_LFOSC is connected to both IPConnect tile (25, 29) output <span style="font-family:monospace">slf_op_0</span> and to the <span style="font-family:monospace">padin</span>
+ of <span style="font-family:monospace">glb_netwk_5</span>.</p>
+
+<p>SB_LFOSC has no configuration bits.</p>
+
+<h2>SPRAM</h2>
+<p>The UltraPlus devices have 1Mbit of extra single-ported RAM, split into 4 256kbit blocks. The full list of connections for each SPRAM block in the 5k device is shown below,
+ as well as the location of the 1 configuration bit which is set to enable use of that SPRAM block.</p>
+
+ <table class="ctab">
+ <tr><th>Signal</th><th>SPRAM (0, 0, 1)</th><th>SPRAM (0, 0, 2)</th><th>SPRAM (25, 0, 3)</th><th>SPRAM (25, 0, 4)</th></tr>
+ <tr><td>ADDRESS[1:0]</td><td>(0, 2, lutff_[1:0]/in_1)</td><td>(0, 2, lutff_[7:6]/in_0)</td><td>(25, 2, lutff_[1:0]/in_1)</td><td>(25, 2, lutff_[7:6]/in_0)</td></tr>
+ <tr><td>ADDRESS[7:2]</td><td>(0, 2, lutff_[7:2]/in_1)</td><td>(0, 3, lutff_[5:0]/in_3)</td><td>(25, 2, lutff_[7:2]/in_1)</td><td>(25, 3, lutff_[5:0]/in_3)</td></tr>
+ <tr><td>ADDRESS[9:8]</td><td>(0, 2, lutff_[1:0]/in_0)</td><td>(0, 3, lutff_[7:6]/in_3)</td><td>(25, 2, lutff_[1:0]/in_0)</td><td>(25, 3, lutff_[7:6]/in_3)</td></tr>
+ <tr><td>ADDRESS[13:10]</td><td>(0, 2, lutff_[5:2]/in_0)</td><td>(0, 3, lutff_[3:0]/in_1)</td><td>(25, 2, lutff_[5:2]/in_0)</td><td>(25, 3, lutff_[3:0]/in_1)</td></tr>
+ <tr><td>DATAIN[7:0]</td><td>(0, 1, lutff_[7:0]/in_3)</td><td>(0, 1, lutff_[7:0]/in_0)</td><td>(25, 1, lutff_[7:0]/in_3)</td><td>(25, 1, lutff_[7:0]/in_0)</td></tr>
+ <tr><td>DATAIN[15:8]</td><td>(0, 1, lutff_[7:0]/in_1)</td><td>(0, 2, lutff_[7:0]/in_3)</td><td>(25, 1, lutff_[7:0]/in_1)</td><td>(25, 2, lutff_[7:0]/in_3)</td></tr>
+ <tr><td>MASKWREN[3:0]</td><td>(0, 3, lutff_[3:0]/in_0)</td><td>(0, 3, lutff_[7:4]/in_0)</td><td>(25, 3, lutff_[3:0]/in_0)</td><td>(25, 3, lutff_[7:4]/in_0)</td></tr>
+ <tr><td>WREN</td><td>(0, 3, lutff_4/in_1)</td><td>(0, 3, lutff_5/in_1)</td><td>(25, 3, lutff_4/in_1)</td><td>(25, 3, lutff_5/in_1)</td></tr>
+ <tr><td>CHIPSELECT</td><td>(0, 3, lutff_6/in_1)</td><td>(0, 3, lutff_7/in_1)</td><td>(25, 3, lutff_6/in_1)</td><td>(25, 3, lutff_7/in_1)</td></tr>
+ <tr><td>CLOCK</td><td>(0, 1, clk)</td><td>(0, 2, clk)</td><td>(25, 1, clk)</td><td>(25, 2, clk)</td></tr>
+ <tr><td>STANDBY</td><td>(0, 4, lutff_0/in_3)</td><td>(0, 4, lutff_1/in_3)</td><td>(25, 4, lutff_0/in_3)</td><td>(25, 4, lutff_1/in_3)</td></tr>
+ <tr><td>SLEEP</td><td>(0, 4, lutff_2/in_3)</td><td>(0, 4, lutff_3/in_3)</td><td>(25, 4, lutff_2/in_3)</td><td>(25, 4, lutff_3/in_3)</td></tr>
+ <tr><td>POWEROFF</td><td>(0, 4, lutff_4/in_3)</td><td>(0, 4, lutff_5/in_3)</td><td>(25, 4, lutff_4/in_3)</td><td>(25, 4, lutff_5/in_3)</td></tr>
+ <tr><td>DATAOUT[7:0]</td><td>(0, 1, slf_op_[7:0])</td><td>(0, 3, slf_op_[7:0])</td><td>(25, 1, slf_op_[7:0])</td><td>(25, 3, slf_op_[7:0])</td></tr>
+ <tr><td>DATAOUT[15:8]</td><td>(0, 2, slf_op_[7:0])</td><td>(0, 4, slf_op_[7:0])</td><td>(25, 2, slf_op_[7:0])</td><td>(25, 4, slf_op_[7:0])</td></tr>
+ <tr><td><em>SPRAM_ENABLE</em></td><td><em>(0, 1, CBIT_0)</em></td><td><em>(0, 1, CBIT_1)</em></td><td><em>(25, 1, CBIT_0)</em></td><td><em>(25, 1, CBIT_1)</em></td></tr>
+ </table>
+
+<h2>RGB LED Driver</h2>
+<p>The UltraPlus devices contain an internal 3-channel 2-24mA constant-current driver intended for RGB led driving (<span style="font-family:monospace">SB_RGBA_DRV</span>). It is broken out onto 3 pins: 39, 40 and 41 on the QFN48 package.
+The LED driver is implemented using the IPConnect tiles and is entirely seperate to the IO cells, if the LED driver is ignored or disabled on a pin then the pin
+can be used as an open-drain IO using the standard IO cell.</p>
+<p>Note that the UltraPlus devices also have a seperate PWM generator IP core, which would often be connected to this one to create LED effects such as "breathing" without
+ involving FPGA resources.</p>
+<p>The LED driver connections are shown in the label below.</p>
+<table class="ctab">
+<tr><th>Signal</th><th>Net</th></tr>
+<tr><td>CURREN</td><td>(25, 29, lutff_6/in_3)</td></tr>
+<tr><td>RGBLEDEN</td><td>(0, 30, lutff_1/in_1)</td></tr>
+<tr><td>RGB0PWM</td><td>(0, 30, lutff_2/in_1)</td></tr>
+<tr><td>RGB1PWM</td><td>(0, 30, lutff_3/in_1)</td></tr>
+<tr><td>RGB2PWM</td><td>(0, 30, lutff_4/in_1)</td></tr>
+</table>
+<p>The configuration bits are as follows. As well as the documented bits, another bit <span style="font-family:monospace">RGBA_DRV_EN</span> is set if any of the channels are enabled.</p>
+<table class="ctab">
+
+<tr><th>Parameter</th><th>Bit</th></tr>
+<tr><td>RGBA_DRV_EN</td><td>(0, 28, CBIT_5)</td></tr>
+<tr><td>RGB0_CURRENT[1:0]</td><td>(0, 28, CBIT_[7:6])</td></tr>
+<tr><td>RGB0_CURRENT[5:2]</td><td>(0, 29, CBIT_[3:0])</td></tr>
+<tr><td>RGB1_CURRENT[3:0]</td><td>(0, 29, CBIT_[7:4])</td></tr>
+<tr><td>RGB1_CURRENT[5:4]</td><td>(0, 30, CBIT_[1:0])</td></tr>
+<tr><td>RGB2_CURRENT[5:0]</td><td>(0, 30, CBIT_[7:2])</td></tr>
+<tr><td>CURRENT_MODE</td><td>(0, 28, CBIT_4)</td></tr>
+
+</table>
+
+<h2>IO Changes</h2>
+<p>The IO tiles contain a few new bits compared to earlier ice40 devices.
+ The bits <span style="font-family:monospace">padeb_test_0</span> and
+ <span style="font-family:monospace">padeb_test_1</span> are set for all pins,
+ even unused ones, unless set as an output.</p>
+<p>There are also some new bits used to control the pullup strength:</p>
+<table class="ctab">
+<tr><th>Strength</th><th>Cell 0</th><th>Cell 1</th></tr>
+<tr><td>3.3k&Omega;</td><td>cf_bit_32<br/>B7[10]</td><td>cf_bit_36<br/>B13[10]</td></tr>
+<tr><td>6.8k&Omega;</td><td>cf_bit_33<br/>B6[10]</td><td>cf_bit_37<br/>B12[10]</td></tr>
+<tr><td>10k&Omega;</td><td>cf_bit_34<br/>B7[15]</td><td>cf_bit_38<br/>B13[15]</td></tr>
+<tr><td>100k&Omega;<br/>(default)</td><td>!cf_bit_35<br/>!B6[15]</td><td>!cf_bit_39<br/>!B12[15]</td></tr>
+
+</table>
+</body></html>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-22 15:19:27 +0000