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Merge pull request #129 from daveshah1/icetime_ufix
Clifford Wolf
2018-02-28
1
-4
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+10
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Fix handling of a port name like CLKHF_FABRIC in icetime
David Shah
2018-02-28
1
-4
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+10
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Merge pull request #126 from daveshah1/icetime_bfix
Clifford Wolf
2018-02-20
1
-4
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+8
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Properly ignore unsupported cell types
David Shah
2018-02-19
1
-4
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+8
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Merge pull request #124 from daveshah1/ultra
Clifford Wolf
2018-02-14
1
-2
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+26
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Add iCE40 Ultra (ice5lp) support to icepack
David Shah
2018-02-13
1
-2
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+26
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Merge pull request #123 from daveshah1/up5k_io
Clifford Wolf
2018-02-13
1
-1
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+14
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Add UltraPlus I³C IO to chipdb
David Shah
2018-02-09
1
-1
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+10
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Add RGB driver outputs to chipdb
David Shah
2018-02-09
1
-0
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+4
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Fix compiler warning (comparison between signed and unsigned int) in icetime
Clifford Wolf
2018-02-09
1
-1
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+1
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Merge pull request #122 from daveshah1/iceprog-up2
Clifford Wolf
2018-02-09
1
-3
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+3
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Add out-of-the-box FT232H support (for Upduino 2, etc)
David Shah
2018-02-09
1
-3
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+3
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Remove up5k_mac16 "example" and add README to up5k_rgb and icebreaker
Clifford Wolf
2018-02-06
6
-123
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+4
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Add icebreaker example project
Clifford Wolf
2018-02-06
4
-0
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+153
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Merge pull request #119 from daveshah1/up5k_improve
Clifford Wolf
2018-01-30
12
-3503
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+18362
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Tidy up
David Shah
2018-01-30
3
-1154
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+0
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Misc UltraPlus fixes
David Shah
2018-01-30
1
-29
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+35
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Updated 5k timing data, icetime regression fix
David Shah
2018-01-29
6
-12479
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+13778
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DSP related fixes
David Shah
2018-01-28
2
-269
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+2
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Working DSP timing analysis
David Shah
2018-01-26
2
-3
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+33
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Work on timing analysis of DSPs
David Shah
2018-01-26
1
-8
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+196
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Parse extra cells in icetime
David Shah
2018-01-23
1
-1
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+50
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More DSP timing fuzzing, start adding new tiles to icetime
David Shah
2018-01-22
3
-2
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+3710
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Seperate different DSP configs in timing data
David Shah
2018-01-22
11
-2532
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+13532
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Merge pull request #118 from daveshah1/up5k_fix_timing
Clifford Wolf
2018-01-20
2
-143
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+88
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Fix 5k timing data
David Shah
2018-01-20
2
-143
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+88
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Merge pull request #116 from daveshah1/up5k_misc_fixes
Clifford Wolf
2018-01-16
14
-10109
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+270
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Add example for 5k UWG30 package
David Shah
2018-01-16
2
-0
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+39
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I³C IO reverse engineered and documented
David Shah
2018-01-16
3
-0
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+56
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Add 5k UWG30 ieren data to db
David Shah
2018-01-16
1
-1
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+5
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Remove seperate 5k RAM DB and share with 8k instead
David Shah
2018-01-16
7
-10016
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+13
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Add pinout for 5k UWG30 package
David Shah
2018-01-16
1
-0
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+23
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Add SPI enable bits to docs
David Shah
2018-01-16
1
-0
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+4
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HFOSC trimming info
David Shah
2018-01-16
2
-1
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+20
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New UltraPlus corner tracing algorithm
David Shah
2018-01-16
1
-87
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+86
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Misc routing tweaks
David Shah
2018-01-16
1
-3
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+7
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Figure out missing SPI config bits, and add to chipdb
David Shah
2018-01-16
3
-2
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+18
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Add "iceprog -e"
Clifford Wolf
2018-01-02
1
-20
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+42
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Merge pull request #113 from cr1901/nosleep
Clifford Wolf
2017-12-31
1
-20
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+65
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Enable writing nosleep config bit into output bitstream.
William D. Jones
2017-12-31
1
-11
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+30
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Add nosleep field to FpgaConfig- read_bits recognizes the option.
William D. Jones
2017-12-31
1
-9
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+35
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Merge pull request #112 from mithro/patch-2
Clifford Wolf
2017-12-09
1
-0
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+13
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Creating COPYING file.
Tim Ansell
2017-12-08
1
-0
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+13
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Merge pull request #110 from daveshah1/up5k_ip
Clifford Wolf
2017-11-28
20
-14
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+5004
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Whitespace fixes
David Shah
2017-11-28
3
-9
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+36
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Add uncommitted changes and tidy up some files
David Shah
2017-11-28
3
-2
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+253
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Chipdb fix for hard IP
David Shah
2017-11-26
1
-4
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+4
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Add note about glitch filter
David Shah
2017-11-25
1
-2
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+12
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Add UltraPlus IP to chipdb
David Shah
2017-11-24
2
-3
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+212
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Initial 5k support in icetime (no support for new cells yet)
David Shah
2017-11-24
3
-7
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+28
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