From 1fefe355459123f7c253a4ac649ccb584a080459 Mon Sep 17 00:00:00 2001
From: Roland Lutz
-A top/bottom io cell has 16 connections named span4_vert_l_0 to span4_vert_l_15 on its top edge and -16 connections named span4_vert_r_0 to span4_vert_r_15 on its bottom edge. The nets span4_vert_l_0 -to span4_vert_l_11 are connected to span4_vert_r_4 to span4_vert_r_15. The span-4 and span-12 wires +A top/bottom io cell has 16 connections named span4_horz_l_0 to span4_horz_l_15 on its left edge and +16 connections named span4_horz_r_0 to span4_horz_r_15 on its right edge. The nets span4_horz_l_0 +to span4_horz_l_11 are connected to span4_horz_r_4 to span4_horz_r_15. The span-4 and span-12 wires of the adjacent logic cell are connected to the nets span4_vert_0 to span4_vert_47 and span12_vert_0 to span12_vert_23.
@@ -489,9 +489,9 @@ of the 1k chip:-- cgit v1.2.3