From 1fefe355459123f7c253a4ac649ccb584a080459 Mon Sep 17 00:00:00 2001 From: Roland Lutz Date: Wed, 7 Jun 2017 16:30:29 +0200 Subject: Fix I/O tile documentation --- docs/io_tile.html | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/io_tile.html b/docs/io_tile.html index c683ff7..82cf65b 100644 --- a/docs/io_tile.html +++ b/docs/io_tile.html @@ -47,9 +47,9 @@ to span12_horz_23.

-A top/bottom io cell has 16 connections named span4_vert_l_0 to span4_vert_l_15 on its top edge and -16 connections named span4_vert_r_0 to span4_vert_r_15 on its bottom edge. The nets span4_vert_l_0 -to span4_vert_l_11 are connected to span4_vert_r_4 to span4_vert_r_15. The span-4 and span-12 wires +A top/bottom io cell has 16 connections named span4_horz_l_0 to span4_horz_l_15 on its left edge and +16 connections named span4_horz_r_0 to span4_horz_r_15 on its right edge. The nets span4_horz_l_0 +to span4_horz_l_11 are connected to span4_horz_r_4 to span4_horz_r_15. The span-4 and span-12 wires of the adjacent logic cell are connected to the nets span4_vert_0 to span4_vert_47 and span12_vert_0 to span12_vert_23.

@@ -489,9 +489,9 @@ of the 1k chip: 1 0faboutBYPASS 2 0faboutRESETB 5 0faboutLATCHINPUTVALUE -12 1neigh_op_bnl_1SDO +12 1neigh_op_bnr_3SDO 4 0faboutSDI -5 0faboutSCLK +3 0faboutSCLK

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