From 2ccae0d3864fd7268118287a85963c0116745cff Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 8 Aug 2019 17:07:52 +0200 Subject: Only dump memory initialization in icebox_vlog if present in ASC file, fixes #228 Signed-off-by: Clifford Wolf --- icebox/icebox_vlog.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py index 184cb03..a2c7950 100755 --- a/icebox/icebox_vlog.py +++ b/icebox/icebox_vlog.py @@ -750,8 +750,9 @@ for tile in ic.ramb_tiles: text_func.append("SB_RAM40_4K%s%s #(" % ("NR" if negclk_rd else "", "NW" if negclk_wr else "")); text_func.append(" .READ_MODE(%d)," % ((1 if get_ram_config('CBIT_2') else 0) + (2 if get_ram_config('CBIT_3') else 0))); text_func.append(" .WRITE_MODE(%d)," % ((1 if get_ram_config('CBIT_0') else 0) + (2 if get_ram_config('CBIT_1') else 0))); - for i in range(16): - text_func.append(" .INIT_%X(256'h%s)%s" % (i, ic.ram_data[tile][i], "," if i < 15 else "")); + if tile in ic.ram_data: + for i in range(16): + text_func.append(" .INIT_%X(256'h%s)%s" % (i, ic.ram_data[tile][i], "," if i < 15 else "")); text_func.append(") ram40_%d_%d (" % tile); text_func.append(" .WADDR(%s)," % get_ram_wire('WADDR', 10, 0)) text_func.append(" .RADDR(%s)," % get_ram_wire('RADDR', 10, 0)) -- cgit v1.2.3