From 8906886e7095e56d50880a40401508a0997fd441 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 7 Feb 2016 10:19:29 +0100 Subject: Website updates --- docs/index.html | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 63 insertions(+), 5 deletions(-) (limited to 'docs') diff --git a/docs/index.html b/docs/index.html index 5cbcb56..caf7152 100644 --- a/docs/index.html +++ b/docs/index.html @@ -1,5 +1,16 @@ + Project IceStorm

Project IceStorm

@@ -48,11 +59,41 @@ HX1K-TQ144 and the iCE40 HX8K-CT256 using our icebox_vlog tool.

-Current work focuses on improvements in our timing analysis flow and support -for all iCE40 LP/HX 1K, 4K, and 8K devices. +Here is a list of currently supported parts and the corresponding options for arachne-pnr (place and route) and icetime (timing analysis):

What is the Status of the Fully Open Source iCE40 Flow?

+ + + + + + + + + + + + + + + + + + + + + + + + + +

Part	Package	Pin Spacing	I/Os	arachne-pnr opts	icetime opts
iCE40-LP1K-SWG16TR	16-ball WLCSP (1.40 x 1.48 mm)	0.35 mm	10	-d 1k -P swg16tr	-d lp1k
iCE40-LP1K-CM36	36-ball ucBGA (2.5 x 2.5 mm)	0.40 mm	25	-d 1k -P cm36	-d lp1k
iCE40-LP1K-CM49	49-ball ucBGA (3 x 3 mm)	0.40 mm	35	-d 1k -P cm49	-d lp1k
iCE40-LP1K-CM81	81-ball ucBGA (4 x 4 mm)	0.40 mm	63	-d 1k -P cm81	-d lp1k
iCE40-LP4K-CM81	81-ball ucBGA (4 x 4 mm)	0.40 mm	63	-d 8k -P cm81:4k	-d lp8k
iCE40-LP8K-CM81	81-ball ucBGA (4 x 4 mm)	0.40 mm	63	-d 8k -P cm81	-d lp8k
iCE40-LP1K-CM121	121-ball ucBGA (5 x 5 mm)	0.40 mm	95	-d 1k -P cm121	-d lp1k
iCE40-LP4K-CM121	121-ball ucBGA (5 x 5 mm)	0.40 mm	93	-d 8k -P cm121:4k	-d lp8k
iCE40-LP8K-CM121	121-ball ucBGA (5 x 5 mm)	0.40 mm	93	-d 8k -P cm121	-d lp8k
iCE40-LP4K-CM225	225-ball ucBGA (7 x 7 mm)	0.40 mm	167	-d 8k -P cm225:4k	-d lp8k
iCE40-LP8K-CM225	225-ball ucBGA (7 x 7 mm)	0.40 mm	178	-d 8k -P cm225	-d lp8k
iCE40-HX8K-CM225	225-ball ucBGA (7 x 7 mm)	0.40 mm	178	-d 8k -P cm225	-d hx8k
iCE40-LP1K-QN84	84-pin QFNS (7 x 7 mm)	0.50 mm	67	-d 1k -P qn84	-d lp1k
iCE40-LP1K-CB81	81-ball csBGA (5 x 5 mm)	0.50 mm	62	-d 1k -P cb81	-d lp1k
iCE40-LP1K-CB121	121-ball csBGA (6 x 6 mm)	0.50 mm	92	-d 1k -P cb121	-d lp1k
iCE40-LP1K-CB121	121-ball csBGA (6 x 6 mm)	0.50 mm	92	-d 1k -P cb121	-d lp1k
iCE40-HX1K-CB132	132-ball csBGA (8 x 8 mm)	0.50 mm	95	-d 1k -P cb132	-d hx1k
iCE40-HX4K-CB132	132-ball csBGA (8 x 8 mm)	0.50 mm	95	-d 8k -P cb132:4k	-d hx8k
iCE40-HX8K-CB132	132-ball csBGA (8 x 8 mm)	0.50 mm	95	-d 8k -P cb132	-d hx8k
iCE40-HX1K-VQ100	100-pin VQFP (14 x 14 mm)	0.50 mm	72	-d 1k -P vq100	-d hx1k
iCE40-HX1K-TQ144	144-pin TQFP (20 x 20 mm)	0.50 mm	96	-d 1k -P tq144	-d hx1k
iCE40-HX4K-TQ144	144-pin TQFP (20 x 20 mm)	0.50 mm	107	-d 8k -P tq144:4k	-d hx8k
iCE40-HX8K-CT256	256-ball caBGA (14 x 14 mm)	0.80 mm	206	-d 8k -P ct256	-d hx8k

+ +

+Current work focuses on further improving our timing analysis flow. +

+ +

How do I use the Fully Open Source iCE40 Flow?

Synthesis for iCE40 FPGAs can be done with Yosys. @@ -86,7 +127,7 @@ sudo apt-get install build-essential clang bison flex libreadline-dev \

-Installing the IceStorm Tools (icepack, icebox, iceprog): +Installing the IceStorm Tools (icepack, icebox, iceprog, icetime, chip databases):

git clone https://github.com/cliffordwolf/icestorm.git icestorm
@@ -113,7 +154,7 @@ make -j$(nproc)
 sudo make install

-Note: The Arachne-PNR build depends on files installed by IceStorm. Always rebuild Arachne-PNR +The Arachne-PNR build converts the IceStorm text chip databases into the arachne-pnr binary chip databases. Always rebuild Arachne-PNR after updating your IceStorm installation.

@@ -194,6 +235,23 @@ create an IceStorm ASCII file for the placed and routed design. The IcePack/IceUnpack, IceBox, and IceProg are written by Clifford Wolf. IcePack/IceUnpack is based on a reference implementation provided by Mathias Lasser. IceMulti is written by Marcus Comstedt.

Where do I get support or meet other IceStorm users?

+ +

+If you have a question regarding the IceStorm flow, use the yosys tag on stackoverflow +to ask your question. If your question is a general question about Verilog HDL design, please consider using the +verilog tag on stackoverflow instead. +

+ +

+For general discussions go to the Yosys Subreddit or #yosys on freenode IRC. +

+ +

+If you have a bug report please file an issue on github. (IceStorm Issue Tracker, +Yosys Issue Tracker, Arachne-PNR Issue Tracker) +

Where is the Documentation?

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