From c0a531efe0d15d98267fb7c5339079f8d8b02a40 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 3 Feb 2016 21:37:43 +0100 Subject: Website edits --- docs/index.html | 50 +++++++++++++++++++++++++++++++++----------------- docs/io_tile.html | 2 +- 2 files changed, 34 insertions(+), 18 deletions(-) (limited to 'docs') diff --git a/docs/index.html b/docs/index.html index 15fa690..13dceb6 100644 --- a/docs/index.html +++ b/docs/index.html @@ -18,9 +18,8 @@

Project IceStorm aims at reverse engineering and documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and -creating bitstream files. At the moment the focus of the project is on the -HX1K-TQ144 and HX8K-CT256 devices, but most of the information is -device-independent. +creating bitstream files. The focus of the project is on the iCE40 1K and +8K chips. (Most of the work was done on HX1K-TQ144 and HX8K-CT256 parts.)

Why the Lattice iCE40?

@@ -32,23 +31,25 @@ reverse engineering and as a reference platform for general purpose FPGA tool de

-Also, with the iCEstick there is +Also, with the Lattice iCEstick there is a cheap and easy to use development platform available, which makes the part interesting -for all kinds of projects. +for all kinds of projects. (The iCEstick features an HX1K device. Lattice also sells an iCE40-HX8K +Breakout Board featuring an HX8K chip.)

What is the Status of the Project?

-We have enough bits mapped that we can create a functional Verilog model for -almost all bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 -and the iCE40 HX8K-CT256, and can create bitstreams for this parts using our -own tool-chain. +We are pretty confident that we have the 1K and 8K devices completely reverse +engineered. For example, it seems we can create correct functional Verilog +models for all bitstreams generated by Lattice iCEcube2 for the iCE40 +HX1K-TQ144 and the iCE40 HX8K-CT256 using our icebox_vlog tool.

-The next milestones for the project are timing analysis and support for more -parts from the iCE40 family. +Current work focuses on improvements in our timing analysis flow and support +for all iCE40 LP/HX 1K, 4K, and 8K devices.

What is the Status of the Fully Open Source iCE40 Flow?

@@ -66,6 +67,12 @@ arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.asc icepack rot.asc rot.bin iceprog rot.bin +

+A simple timing analysis report can be generated using the icetime utility: +

+ +
icetime -tmd hx1k rot.asc
+

Where are the Tools? How to install?

@@ -125,25 +132,34 @@ share regarding the install procedures on the operating system of your choice.

What are the IceStorm Tools?

+

+The IceStorm Tools are a couple of small programs for working with iCE40 bitstream files and our +ASCII representation of it. The complete Open Source iCE40 Flow consists of the IceStorm Tools, Arachne-PNR, and Yosys. +

+

IcePack/IceUnpack

-The iceunpack program converts an iCE40 .bin file into the IceBox ASCII format +The iceunpack program converts an iCE40 .bin file into the IceStorm ASCII format that has blocks of 0 and 1 for the config bits for each tile in the chip. The -icepack program converts such an ASCII file back to an iCE40 .bin file. +icepack program converts such an ASCII file back to an iCE40 .bin file. All +other IceStorm Tools operate on the ASCII file format, not the bitstream binaries.

IceTime

-The icetime program is an iCE40 timing analysis tool. It reads designs in IceBox ASCII format and writes times timing +The icetime program is an iCE40 timing analysis tool. It reads designs in IceStorm ASCII format and writes times timing netlists that can be used in external timing analysers. It also includes a simple topological timing analyser that can be used to create timing reports.

IceBox

-A python library and various tools for working with IceBox ASCII files and accessing +A python library and various tools for working with IceStorm ASCII files and accessing the device database. For example icebox_vlog converts our ASCII file dump of a bitstream into a Verilog file that implements an equivalent circuit.

@@ -165,7 +181,7 @@ A tool for packing multiple bitstream files into one iCE40 multiboot image file.

The IceStorm Makefile builds and installs two files: chipdb-1k.txt and chipdb-8k.txt. This files contain all the relevant information for arachne-pnr to place&route a design and -create an IceBox ASCII file for the placed and routed design. +create an IceStorm ASCII file for the placed and routed design.

@@ -423,7 +439,7 @@ e.g. using the following BibTeX code:

Documentation mostly by Clifford Wolf <clifford@clifford.at> in 2015. Based on research by Mathias Lasser and Clifford Wolf.
-Buy an iCEstick from Lattice and see what you can do with the information provided here. +Buy an iCEstick or iCE40-HX8K Breakout Board from Lattice and see what you can do with the tools and information provided here.

diff --git a/docs/io_tile.html b/docs/io_tile.html index 1a5ca61..c683ff7 100644 --- a/docs/io_tile.html +++ b/docs/io_tile.html @@ -293,7 +293,7 @@ tile are used. In IceBox nomenclature such bits are called "extra bits".

The following table lists which pins / IO blocks may be used to drive -which global net, and what .extra statements in the IceBox ASCII file +which global net, and what .extra statements in the IceStorm ASCII file format to represent the corresponding configuration bits:

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