From ca6b2d9ebd521ecec58b9b5627c9380355adeab1 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 10 Jun 2018 17:14:04 +0200
Subject: Fix "routing" vs "buffer" documentation

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 docs/logic_tile.html | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

(limited to 'docs')

diff --git a/docs/logic_tile.html b/docs/logic_tile.html
index ab9adc7..94df5a9 100644
--- a/docs/logic_tile.html
+++ b/docs/logic_tile.html
@@ -29,15 +29,9 @@ The <i>span-4</i> and <i>span-12</i> wires are the main interconnect resource in
 </p>
 
 <p>
-The bits marked <span style="font-family:monospace">routing</span> in the bitstream enable switches (transfer gates) that can
-be used to connect wire segments bidirectionally to each other in order to create larger
-segments. The bits marked <span style="font-family:monospace">buffer</span> in the bitstream enable tristate buffers that drive
-the signal in one direction from one wire to another. Both types of bits exist for routing between
-span-wires. See the auto generated documentation for the LOGIC Tile configuration bits for details.
-</p>
-
-<p>
-Only directional tristate buffers are used to route signals between the span-wires and the logic cells.
+All routing resources in iCE40 are directional tristate buffers. The bits marked <span style="font-family:monospace">routing</span>
+use the all-zeros config pattern for tristate, while the bits marked <span style="font-family:monospace">buffer</span> have
+a dedicated buffer-enable bit, which is 1 in all non-tristate configurations.
 </p>
 
 <h3 style="clear:both">Span-4 Horizontal</h3>
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