From f920831e43c686dcaeca39c2481d5f22c014940f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 9 Jan 2017 21:21:15 +0100 Subject: Some cleanups in verilog examples --- examples/hx8kboard/example.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'examples/hx8kboard') diff --git a/examples/hx8kboard/example.v b/examples/hx8kboard/example.v index accbc2e..69a446f 100644 --- a/examples/hx8kboard/example.v +++ b/examples/hx8kboard/example.v @@ -16,7 +16,7 @@ module top ( reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; - always@(posedge clk) begin + always @(posedge clk) begin counter <= counter + 1; outcnt <= counter >> LOG2DELAY; end -- cgit v1.2.3