From 94aa596cb144cc47dc054377e1510fbb4effbfd8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 11 Nov 2017 11:26:43 +0000 Subject: Trace DSP routing --- icebox/icebox_explain.py | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'icebox/icebox_explain.py') diff --git a/icebox/icebox_explain.py b/icebox/icebox_explain.py index 50cce09..3b9875f 100755 --- a/icebox/icebox_explain.py +++ b/icebox/icebox_explain.py @@ -166,6 +166,13 @@ for idx in ic.ramb_tiles: for idx in ic.ramt_tiles: print_tile(".ramt_tile %d %d" % idx, ic, idx[0], idx[1], ic.ramt_tiles[idx], ic.tile_db(idx[0], idx[1])) +for i in range(4): + for idx in ic.dsp_tiles[i]: + print_tile(".dsp%d_tile %d %d" % (i, idx[0], idx[1]), ic, idx[0], idx[1], ic.dsp_tiles[i][idx], ic.tile_db(idx[0], idx[1])) + +for idx in ic.ipcon_tiles: + print_tile(".ipcon_tile %d %d" % idx, ic, idx[0], idx[1], ic.ipcon_tiles[idx], ic.tile_db(idx[0], idx[1])) + for bit in ic.extra_bits: print() print(".extra_bit %d %d %d" % bit) -- cgit v1.2.3 From cdf688363968ee8895d8e6fe08178cff8fc9ee75 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 16 Nov 2017 14:03:11 +0000 Subject: UltraPlus DSPs working --- icebox/icebox_explain.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'icebox/icebox_explain.py') diff --git a/icebox/icebox_explain.py b/icebox/icebox_explain.py index 3b9875f..4e678ff 100755 --- a/icebox/icebox_explain.py +++ b/icebox/icebox_explain.py @@ -117,7 +117,7 @@ def print_tile(stmt, ic, x, y, tile, db): bitinfo.append("") extra_text = "" for i in range(len(line)): - if 36 <= i <= 45 and re.search(r"logic_tile", stmt): + if 36 <= i <= 45 and re.search(r"(logic_tile|dsp\d_tile|ipcon_tile)", stmt): lutff_idx = k // 2 lutff_bitnum = (i-36) + 10*(k%2) if line[i] == "1": -- cgit v1.2.3